Matthias Braun f9317bf0be Fix tied operands in phi-coalescing.mir test; try to adapt MLRegalloc tests ... Fix a test using invalid MLIR using different VRegs for the tied operands of ADD64rr, which happened to trigger an assertion after my latest changes. Also attempting to adjust the MLRegalloc tests to the adjusted regalloc (though I don't have a 100% working setup for them even without my changes)		2022-09-30 17:20:35 -07:00
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AArch64	Fix a fragment overflow problem when composing super-registers.	2022-01-31 09:47:29 -08:00
ARM	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
Hexagon	[RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs	2021-07-14 04:29:42 -07:00
InstrRef	Fix tied operands in phi-coalescing.mir test; try to adapt MLRegalloc tests	2022-09-30 17:20:35 -07:00
Mips	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
SystemZ	…
X86	Reapply "[DebugInfo] Extend the InstrRef LDV to support DbgValues with many Ops"	2022-09-01 14:20:24 +01:00
lit.local.cfg	…