120 lines
3.1 KiB
ArmAsm
120 lines
3.1 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
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##################################
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# Hypervisor Configuration
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##################################
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# henvcfgh
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# name
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# CHECK-INST: csrrs t1, henvcfgh, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x61]
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# CHECK-INST-ALIAS: csrr t1, henvcfgh
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# uimm12
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# CHECK-INST: csrrs t2, henvcfgh, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x61]
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# CHECK-INST-ALIAS: csrr t2, henvcfgh
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# name
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csrrs t1, henvcfgh, zero
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# uimm12
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csrrs t2, 0x61A, zero
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#####################################################
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# Hypervisor Counter/Timer Virtualization Registers
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#####################################################
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# htimedeltah
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# name
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# CHECK-INST: csrrs t1, htimedeltah, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x50,0x61]
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# CHECK-INST-ALIAS: csrr t1, htimedeltah
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# uimm12
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# CHECK-INST: csrrs t2, htimedeltah, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x61]
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# CHECK-INST-ALIAS: csrr t2, htimedeltah
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# name
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csrrs t1, htimedeltah, zero
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# uimm12
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csrrs t2, 0x615, zero
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################################
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# Virtual Supervisor Registers
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################################
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# vstimecmph
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# name
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# CHECK-INST: csrrs t1, vstimecmph, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x25]
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# CHECK-INST-ALIAS: csrr t1, vstimecmph
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# uimm12
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# CHECK-INST: csrrs t2, vstimecmph, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x25]
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# CHECK-INST-ALIAS: csrr t2, vstimecmph
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# name
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csrrs t1, vstimecmph, zero
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# uimm12
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csrrs t2, 0x25D, zero
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#########################################
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# State Enable Extension (Smstateen)
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#########################################
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# hstateen0h
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# name
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# CHECK-INST: csrrs t1, hstateen0h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x61]
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# CHECK-INST-ALIAS: csrr t1, hstateen0h
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# uimm12
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# CHECK-INST: csrrs t2, hstateen0h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x61]
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# CHECK-INST-ALIAS: csrr t2, hstateen0h
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# name
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csrrs t1, hstateen0h, zero
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# uimm12
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csrrs t2, 0x61C, zero
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# hstateen1h
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# name
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# CHECK-INST: csrrs t1, hstateen1h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x61]
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# CHECK-INST-ALIAS: csrr t1, hstateen1h
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# uimm12
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# CHECK-INST: csrrs t2, hstateen1h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x61]
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# CHECK-INST-ALIAS: csrr t2, hstateen1h
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# name
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csrrs t1, hstateen1h, zero
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# uimm12
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csrrs t2, 0x61D, zero
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# hstateen2h
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# name
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# CHECK-INST: csrrs t1, hstateen2h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x61]
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# CHECK-INST-ALIAS: csrr t1, hstateen2h
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# uimm12
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# CHECK-INST: csrrs t2, hstateen2h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x61]
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# CHECK-INST-ALIAS: csrr t2, hstateen2h
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# name
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csrrs t1, hstateen2h, zero
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# uimm12
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csrrs t2, 0x61E, zero
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# hstateen3h
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# name
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# CHECK-INST: csrrs t1, hstateen3h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x61]
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# CHECK-INST-ALIAS: csrr t1, hstateen3h
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# uimm12
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# CHECK-INST: csrrs t2, hstateen3h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x61]
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# CHECK-INST-ALIAS: csrr t2, hstateen3h
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# name
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csrrs t1, hstateen3h, zero
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# uimm12
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csrrs t2, 0x61F, zero
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