OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
llvm-project/llvm/test/tools/llvm-mca/AArch64
History
Matt Devereau 30b045aba6 [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes 
Add some missing patterns for ld1rq's scalar + scalar addressing mode.
Also, adds the scalar + imm and scalar + scalar addressing modes for
the patterns added in https://reviews.llvm.org/D130010

Differential Revision: https://reviews.llvm.org/D130993
 		2022-08-25 13:07:37 +00:00
..
A64FX [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes 2022-08-25 13:07:37 +00:00
Cortex [AArch64] Use Neoverse N2 sched model as default for: 2022-07-08 13:34:13 +00:00
Cyclone
…
Exynos
…
Falkor
…
HiSilicon [AArch64] Fix sched model for tsv110 2022-08-25 19:20:07 +08:00
Neoverse [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes 2022-08-25 13:07:37 +00:00
lit.local.cfg
…