866 lines
30 KiB
TableGen
866 lines
30 KiB
TableGen
//=- ARMSchedCyclone.td - AArch64 Cyclone Scheduling Defs ----*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for AArch64 Cyclone to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def CycloneModel : SchedMachineModel {
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let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
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let MicroOpBufferSize = 192; // Based on the reorder buffer.
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let LoadLatency = 4; // Optimistic load latency.
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let MispredictPenalty = 16; // 14-19 cycles are typical.
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available on Cyclone.
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// 4 integer pipes
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def CyUnitI : ProcResource<4> {
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let BufferSize = 48;
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}
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// 2 branch units: I[0..1]
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def CyUnitB : ProcResource<2> {
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let Super = CyUnitI;
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let BufferSize = 24;
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}
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// 1 indirect-branch unit: I[0]
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def CyUnitBR : ProcResource<1> {
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let Super = CyUnitB;
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}
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// 2 shifter pipes: I[2..3]
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// When an instruction consumes a CyUnitIS, it also consumes a CyUnitI
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def CyUnitIS : ProcResource<2> {
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let Super = CyUnitI;
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let BufferSize = 24;
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}
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// 1 mul pipe: I[0]
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def CyUnitIM : ProcResource<1> {
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let Super = CyUnitBR;
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let BufferSize = 32;
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}
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// 1 div pipe: I[1]
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def CyUnitID : ProcResource<1> {
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let Super = CyUnitB;
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let BufferSize = 16;
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}
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// 1 integer division unit. This is driven by the ID pipe, but only
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// consumes the pipe for one cycle at issue and another cycle at writeback.
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def CyUnitIntDiv : ProcResource<1>;
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// 2 ld/st pipes.
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def CyUnitLS : ProcResource<2> {
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let BufferSize = 28;
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}
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// 3 fp/vector pipes.
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def CyUnitV : ProcResource<3> {
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let BufferSize = 48;
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}
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// 2 fp/vector arithmetic and multiply pipes: V[0-1]
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def CyUnitVM : ProcResource<2> {
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let Super = CyUnitV;
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let BufferSize = 32;
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}
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// 1 fp/vector division/sqrt pipe: V[2]
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def CyUnitVD : ProcResource<1> {
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let Super = CyUnitV;
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let BufferSize = 16;
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}
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// 1 fp compare pipe: V[0]
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def CyUnitVC : ProcResource<1> {
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let Super = CyUnitVM;
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let BufferSize = 16;
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}
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// 2 fp division/square-root units. These are driven by the VD pipe,
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// but only consume the pipe for one cycle at issue and a cycle at writeback.
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def CyUnitFloatDiv : ProcResource<2>;
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//===----------------------------------------------------------------------===//
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// Define scheduler read/write resources and latency on Cyclone.
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// This mirrors sections 7.7-7.9 of the Tuning Guide v1.0.1.
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let SchedModel = CycloneModel in {
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//---
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// 7.8.1. Moves
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//---
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// A single nop micro-op (uX).
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def WriteX : SchedWriteRes<[]> { let Latency = 0; }
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// Move zero is a register rename (to machine register zero).
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// The move is replaced by a single nop micro-op.
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// MOVZ Rd, #0
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// AND Rd, Rzr, #imm
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def WriteZPred : SchedPredicate<[{TII->isGPRZero(MI)}]>;
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def WriteImmZ : SchedWriteVariant<[
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SchedVar<WriteZPred, [WriteX]>,
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SchedVar<NoSchedPred, [WriteImm]>]>;
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def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
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// Move GPR is a register rename and single nop micro-op.
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// ORR Xd, XZR, Xm
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// ADD Xd, Xn, #0
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def WriteIMovPred : SchedPredicate<[{TII->isGPRCopy(MI)}]>;
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def WriteVMovPred : SchedPredicate<[{TII->isFPRCopy(MI)}]>;
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def WriteMov : SchedWriteVariant<[
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SchedVar<WriteIMovPred, [WriteX]>,
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SchedVar<WriteVMovPred, [WriteX]>,
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SchedVar<NoSchedPred, [WriteI]>]>;
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def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>;
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// Move non-zero immediate is an integer ALU op.
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// MOVN,MOVZ,MOVK
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def : WriteRes<WriteImm, [CyUnitI]>;
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//---
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// 7.8.2-7.8.5. Arithmetic and Logical, Comparison, Conditional,
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// Shifts and Bitfield Operations
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//---
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// ADR,ADRP
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// ADD(S)ri,SUB(S)ri,AND(S)ri,EORri,ORRri
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// ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr
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// ADC(S),SBC(S)
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// Aliases: CMN, CMP, TST
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//
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// Conditional operations.
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// CCMNi,CCMPi,CCMNr,CCMPr,
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// CSEL,CSINC,CSINV,CSNEG
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//
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// Bit counting and reversal operations.
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// CLS,CLZ,RBIT,REV,REV16,REV32
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def : WriteRes<WriteI, [CyUnitI]>;
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// ADD with shifted register operand is a single micro-op that
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// consumes a shift pipeline for two cycles.
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// ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
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// EXAMPLE: ADDrs Xn, Xm LSL #imm
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def : WriteRes<WriteISReg, [CyUnitIS]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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// ADD with extended register operand is the same as shifted reg operand.
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// ADD(S)re,SUB(S)re
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// EXAMPLE: ADDXre Xn, Xm, UXTB #1
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def : WriteRes<WriteIEReg, [CyUnitIS]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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// Variable shift and bitfield operations.
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// ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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def : WriteRes<WriteIS, [CyUnitIS]>;
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// EXTR Shifts a pair of registers and requires two micro-ops.
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// The second micro-op is delayed, as modeled by ReadExtrHi.
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// EXTR Xn, Xm, #imm
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def : WriteRes<WriteExtr, [CyUnitIS, CyUnitIS]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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// EXTR's first register read is delayed by one cycle, effectively
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// shortening its writer's latency.
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// EXTR Xn, Xm, #imm
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def : ReadAdvance<ReadExtrHi, 1>;
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//---
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// 7.8.6. Multiplies
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//---
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// MUL/MNEG are aliases for MADD/MSUB.
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// MADDW,MSUBW,SMADDL,SMSUBL,UMADDL,UMSUBL
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def : WriteRes<WriteIM32, [CyUnitIM]> {
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let Latency = 4;
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}
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// MADDX,MSUBX,SMULH,UMULH
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def : WriteRes<WriteIM64, [CyUnitIM]> {
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let Latency = 5;
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}
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//---
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// 7.8.7. Divide
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//---
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// 32-bit divide takes 7-13 cycles. 10 cycles covers a 20-bit quotient.
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// The ID pipe is consumed for 2 cycles: issue and writeback.
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// SDIVW,UDIVW
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def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
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let Latency = 10;
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let ResourceCycles = [2, 10];
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}
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// 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient.
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// The ID pipe is consumed for 2 cycles: issue and writeback.
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// SDIVX,UDIVX
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def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> {
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let Latency = 13;
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let ResourceCycles = [2, 13];
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}
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//---
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// 7.8.8,7.8.10. Load/Store, single element
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//---
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// Integer loads take 4 cycles and use one LS unit for one cycle.
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def : WriteRes<WriteLD, [CyUnitLS]> {
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let Latency = 4;
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}
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// Store-load forwarding is 4 cycles.
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//
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// Note: The store-exclusive sequence incorporates this
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// latency. However, general heuristics should not model the
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// dependence between a store and subsequent may-alias load because
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// hardware speculation works.
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def : WriteRes<WriteST, [CyUnitLS]> {
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let Latency = 4;
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}
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// Load from base address plus an optionally scaled register offset.
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// Rt latency is latency WriteIS + WriteLD.
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// EXAMPLE: LDR Xn, Xm [, lsl 3]
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def CyWriteLDIdx : SchedWriteVariant<[
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SchedVar<ScaledIdxPred, [WriteIS, WriteLD]>, // Load from scaled register.
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SchedVar<NoSchedPred, [WriteLD]>]>; // Load from register offset.
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def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type.
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// EXAMPLE: STR Xn, Xm [, lsl 3]
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def CyWriteSTIdx : SchedWriteVariant<[
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SchedVar<ScaledIdxPred, [WriteIS, WriteST]>, // Store to scaled register.
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SchedVar<NoSchedPred, [WriteST]>]>; // Store to register offset.
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def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type.
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// Read the (unshifted) base register Xn in the second micro-op one cycle later.
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// EXAMPLE: LDR Xn, Xm [, lsl 3]
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def ReadBaseRS : SchedReadAdvance<1>;
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def CyReadAdrBase : SchedReadVariant<[
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SchedVar<ScaledIdxPred, [ReadBaseRS]>, // Read base reg after shifting offset.
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SchedVar<NoSchedPred, [ReadDefault]>]>; // Read base reg with no shift.
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def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
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//---
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// 7.8.9,7.8.11. Load/Store, paired
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//---
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// Address pre/post increment is a simple ALU op with one cycle latency.
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def : WriteRes<WriteAdr, [CyUnitI]>;
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// LDP high register write is fused with the load, but a nop micro-op remains.
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def : WriteRes<WriteLDHi, []> {
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let Latency = 4;
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}
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// STP is a vector op and store, except for QQ, which is just two stores.
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def : SchedAlias<WriteSTP, WriteVSTShuffle>;
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def : InstRW<[WriteST, WriteST], (instrs STPQi)>;
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//---
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// 7.8.13. Branches
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//---
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// Branches take a single micro-op.
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// The misprediction penalty is defined as a SchedMachineModel property.
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def : WriteRes<WriteBr, [CyUnitB]> {let Latency = 0;}
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def : WriteRes<WriteBrReg, [CyUnitBR]> {let Latency = 0;}
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//---
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// 7.8.14. Never-issued Instructions, Barrier and Hint Operations
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//---
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// NOP,SEV,SEVL,WFE,WFI,YIELD
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def : WriteRes<WriteHint, []> {let Latency = 0;}
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// ISB
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def : InstRW<[WriteI], (instrs ISB)>;
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// SLREX,DMB,DSB
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def : WriteRes<WriteBarrier, [CyUnitLS]>;
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// System instructions get an invalid latency because the latency of
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// other operations across them is meaningless.
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def : WriteRes<WriteSys, []> {let Latency = -1;}
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//===----------------------------------------------------------------------===//
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// 7.9 Vector Unit Instructions
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// Simple vector operations take 2 cycles.
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def : WriteRes<WriteV, [CyUnitV]> {let Latency = 2;}
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// Define some longer latency vector op types for Cyclone.
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def CyWriteV3 : SchedWriteRes<[CyUnitV]> {let Latency = 3;}
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def CyWriteV4 : SchedWriteRes<[CyUnitV]> {let Latency = 4;}
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def CyWriteV5 : SchedWriteRes<[CyUnitV]> {let Latency = 5;}
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def CyWriteV6 : SchedWriteRes<[CyUnitV]> {let Latency = 6;}
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// Simple floating-point operations take 2 cycles.
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def : WriteRes<WriteF, [CyUnitV]> {let Latency = 2;}
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//---
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// 7.9.1 Vector Moves
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//---
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// TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently
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// generates expensive int-float conversion instead:
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// FMOVDi Dd, #0.0
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// FMOVv2f64ns Vd.2d, #0.0
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// FMOVSi,FMOVDi
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def : WriteRes<WriteFImm, [CyUnitV]> {let Latency = 2;}
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// MOVI,MVNI are WriteV
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// FMOVv2f32ns,FMOVv2f64ns,FMOVv4f32ns are WriteV
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// Move FPR is a register rename and single nop micro-op.
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// ORR.16b Vd,Vn,Vn
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// COPY is handled above in the WriteMov Variant.
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def WriteVMov : SchedWriteVariant<[
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SchedVar<WriteVMovPred, [WriteX]>,
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SchedVar<NoSchedPred, [WriteV]>]>;
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def : InstRW<[WriteVMov], (instrs ORRv16i8)>;
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// FMOVSr,FMOVDr are WriteF.
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// MOV V,V is a WriteV.
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// CPY D,V[x] is a WriteV
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// INS V[x],V[y] is a WriteV.
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// FMOVWSr,FMOVXDr,FMOVXDHighr
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def : WriteRes<WriteFCopy, [CyUnitLS]> {
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let Latency = 5;
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}
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// FMOVSWr,FMOVDXr
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def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>;
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// INS V[x],R
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def CyWriteCopyToFPR : WriteSequence<[WriteVLD, WriteV]>;
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def : InstRW<[CyWriteCopyToFPR], (instregex "INSv")>;
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// SMOV,UMOV R,V[x]
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def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
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def : InstRW<[CyWriteCopyToGPR], (instregex "SMOVv","UMOVv")>;
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// DUP V,R
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def : InstRW<[CyWriteCopyToFPR], (instregex "DUPv")>;
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// DUP V,V[x] is a WriteV.
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//---
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// 7.9.2 Integer Arithmetic, Logical, and Comparisons
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//---
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// BIC,ORR V,#imm are WriteV
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def : InstRW<[CyWriteV3], (instregex "ABSv")>;
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// MVN,NEG,NOT are WriteV
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def : InstRW<[CyWriteV3], (instregex "SQABSv","SQNEGv")>;
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// ADDP is a WriteV.
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def CyWriteVADDLP : SchedWriteRes<[CyUnitV]> {let Latency = 2;}
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def : InstRW<[CyWriteVADDLP], (instregex "SADDLPv","UADDLPv")>;
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def : InstRW<[CyWriteV3],
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(instregex "ADDVv","SMAXVv","UMAXVv","SMINVv","UMINVv")>;
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def : InstRW<[CyWriteV3], (instregex "SADDLV","UADDLV")>;
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// ADD,SUB are WriteV
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// Forward declare.
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def CyWriteVABD : SchedWriteRes<[CyUnitV]> {let Latency = 3;}
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// Add/Diff and accumulate uses the vector multiply unit.
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def CyWriteVAccum : SchedWriteRes<[CyUnitVM]> {let Latency = 3;}
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def CyReadVAccum : SchedReadAdvance<1,
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[CyWriteVAccum, CyWriteVADDLP, CyWriteVABD]>;
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def : InstRW<[CyWriteVAccum, CyReadVAccum],
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(instregex "SADALP","UADALP")>;
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def : InstRW<[CyWriteVAccum, CyReadVAccum],
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(instregex "SABAv","UABAv","SABALv","UABALv")>;
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def : InstRW<[CyWriteV3], (instregex "SQADDv","SQSUBv","UQADDv","UQSUBv")>;
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def : InstRW<[CyWriteV3], (instregex "SUQADDv","USQADDv")>;
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def : InstRW<[CyWriteV4], (instregex "ADDHNv","RADDHNv", "RSUBHNv", "SUBHNv")>;
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// WriteV includes:
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// AND,BIC,CMTST,EOR,ORN,ORR
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// ADDP
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// SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD
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// SADDL,SSUBL,UADDL,USUBL
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// SADDW,SSUBW,UADDW,USUBW
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def : InstRW<[CyWriteV3], (instregex "CMEQv","CMGEv","CMGTv",
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"CMLEv","CMLTv",
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"CMHIv","CMHSv")>;
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def : InstRW<[CyWriteV3], (instregex "SMAXv","SMINv","UMAXv","UMINv",
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"SMAXPv","SMINPv","UMAXPv","UMINPv")>;
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def : InstRW<[CyWriteVABD], (instregex "SABDv","UABDv",
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"SABDLv","UABDLv")>;
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//---
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// 7.9.3 Floating Point Arithmetic and Comparisons
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//---
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// FABS,FNEG are WriteF
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def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>;
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def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>;
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def : InstRW<[CyWriteV3], (instregex "FMAXPv2i","FMAXNMPv2i",
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"FMINPv2i","FMINNMPv2i")>;
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def : InstRW<[CyWriteV4], (instregex "FMAXVv","FMAXNMVv","FMINVv","FMINNMVv")>;
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def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32,
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FSUBSrr,FSUBv2f32,FSUBv4f32,
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FADDPv2f32,FADDPv4f32,
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FABD32,FABDv2f32,FABDv4f32)>;
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def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64,
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FSUBDrr,FSUBv2f64,
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FADDPv2f64,
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FABD64,FABDv2f64)>;
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def : InstRW<[CyWriteV3], (instregex "FCMEQ","FCMGT","FCMLE","FCMLT")>;
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def : InstRW<[CyWriteV3], (instregex "FACGE","FACGT",
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"FMAXS","FMAXD","FMAXv",
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"FMINS","FMIND","FMINv",
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"FMAXNMS","FMAXNMD","FMAXNMv",
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"FMINNMS","FMINNMD","FMINNMv",
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"FMAXPv2f","FMAXPv4f",
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"FMINPv2f","FMINPv4f",
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"FMAXNMPv2f","FMAXNMPv4f",
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"FMINNMPv2f","FMINNMPv4f")>;
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// FCMP,FCMPE,FCCMP,FCCMPE
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def : WriteRes<WriteFCmp, [CyUnitVC]> {let Latency = 4;}
|
|
|
|
// FCSEL is a WriteF.
|
|
|
|
//---
|
|
// 7.9.4 Shifts and Bitfield Operations
|
|
//---
|
|
|
|
// SHL is a WriteV
|
|
|
|
def CyWriteVSHR : SchedWriteRes<[CyUnitV]> {let Latency = 2;}
|
|
def : InstRW<[CyWriteVSHR], (instregex "SSHRv","USHRv")>;
|
|
|
|
def CyWriteVSRSHR : SchedWriteRes<[CyUnitV]> {let Latency = 3;}
|
|
def : InstRW<[CyWriteVSRSHR], (instregex "SRSHRv","URSHRv")>;
|
|
|
|
// Shift and accumulate uses the vector multiply unit.
|
|
def CyWriteVShiftAcc : SchedWriteRes<[CyUnitVM]> {let Latency = 3;}
|
|
def CyReadVShiftAcc : SchedReadAdvance<1,
|
|
[CyWriteVShiftAcc, CyWriteVSHR, CyWriteVSRSHR]>;
|
|
def : InstRW<[CyWriteVShiftAcc, CyReadVShiftAcc],
|
|
(instregex "SRSRAv","SSRAv","URSRAv","USRAv")>;
|
|
|
|
// SSHL,USHL are WriteV.
|
|
|
|
def : InstRW<[CyWriteV3], (instregex "SRSHLv","URSHLv")>;
|
|
|
|
// SQSHL,SQSHLU,UQSHL are WriteV.
|
|
|
|
def : InstRW<[CyWriteV3], (instregex "SQRSHLv","UQRSHLv")>;
|
|
|
|
// WriteV includes:
|
|
// SHLL,SSHLL,USHLL
|
|
// SLI,SRI
|
|
// BIF,BIT,BSL
|
|
// EXT
|
|
// CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
|
// XTN2
|
|
|
|
def : InstRW<[CyWriteV4],
|
|
(instregex "RSHRNv","SHRNv",
|
|
"SQRSHRNv","SQRSHRUNv","SQSHRNv","SQSHRUNv",
|
|
"UQRSHRNv","UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>;
|
|
|
|
//---
|
|
// 7.9.5 Multiplication
|
|
//---
|
|
|
|
def CyWriteVMul : SchedWriteRes<[CyUnitVM]> { let Latency = 4;}
|
|
def : InstRW<[CyWriteVMul], (instregex "MULv","SMULLv","UMULLv",
|
|
"SQDMULLv","SQDMULHv","SQRDMULHv")>;
|
|
|
|
// FMUL,FMULX,FNMUL default to WriteFMul.
|
|
def : WriteRes<WriteFMul, [CyUnitVM]> { let Latency = 4;}
|
|
|
|
def CyWriteV64Mul : SchedWriteRes<[CyUnitVM]> { let Latency = 5;}
|
|
def : InstRW<[CyWriteV64Mul], (instrs FMULDrr,FMULv2f64,FMULv2i64_indexed,
|
|
FNMULDrr,FMULX64,FMULXv2f64,FMULXv2i64_indexed)>;
|
|
|
|
def CyReadVMulAcc : SchedReadAdvance<1, [CyWriteVMul, CyWriteV64Mul]>;
|
|
def : InstRW<[CyWriteVMul, CyReadVMulAcc],
|
|
(instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
|
|
"SQDMLAL","SQDMLSL")>;
|
|
|
|
def CyWriteSMul : SchedWriteRes<[CyUnitVM]> { let Latency = 8;}
|
|
def CyWriteDMul : SchedWriteRes<[CyUnitVM]> { let Latency = 10;}
|
|
def CyReadSMul : SchedReadAdvance<4, [CyWriteSMul]>;
|
|
def CyReadDMul : SchedReadAdvance<5, [CyWriteDMul]>;
|
|
|
|
def : InstRW<[CyWriteSMul, CyReadSMul],
|
|
(instrs FMADDSrrr,FMSUBSrrr,FNMADDSrrr,FNMSUBSrrr,
|
|
FMLAv2f32,FMLAv4f32,
|
|
FMLAv1i32_indexed,FMLAv1i64_indexed,FMLAv2i32_indexed)>;
|
|
def : InstRW<[CyWriteDMul, CyReadDMul],
|
|
(instrs FMADDDrrr,FMSUBDrrr,FNMADDDrrr,FNMSUBDrrr,
|
|
FMLAv2f64,FMLAv2i64_indexed,
|
|
FMLSv2f64,FMLSv2i64_indexed)>;
|
|
|
|
def CyWritePMUL : SchedWriteRes<[CyUnitVD]> { let Latency = 3; }
|
|
def : InstRW<[CyWritePMUL], (instregex "PMULv", "PMULLv")>;
|
|
|
|
//---
|
|
// 7.9.6 Divide and Square Root
|
|
//---
|
|
|
|
// FDIV,FSQRT
|
|
// TODO: Add 64-bit variant with 19 cycle latency.
|
|
// TODO: Specialize FSQRT for longer latency.
|
|
def : WriteRes<WriteFDiv, [CyUnitVD, CyUnitFloatDiv]> {
|
|
let Latency = 17;
|
|
let ResourceCycles = [2, 17];
|
|
}
|
|
|
|
def : InstRW<[CyWriteV4], (instregex "FRECPEv","FRECPXv","URECPEv","URSQRTEv")>;
|
|
|
|
def WriteFRSQRTE : SchedWriteRes<[CyUnitVM]> { let Latency = 4; }
|
|
def : InstRW<[WriteFRSQRTE], (instregex "FRSQRTEv")>;
|
|
|
|
def WriteFRECPS : SchedWriteRes<[CyUnitVM]> { let Latency = 8; }
|
|
def WriteFRSQRTS : SchedWriteRes<[CyUnitVM]> { let Latency = 10; }
|
|
def : InstRW<[WriteFRECPS], (instregex "FRECPSv")>;
|
|
def : InstRW<[WriteFRSQRTS], (instregex "FRSQRTSv")>;
|
|
|
|
//---
|
|
// 7.9.7 Integer-FP Conversions
|
|
//---
|
|
|
|
// FCVT lengthen f16/s32
|
|
def : InstRW<[WriteV], (instrs FCVTSHr,FCVTDHr,FCVTDSr)>;
|
|
|
|
// FCVT,FCVTN,FCVTXN
|
|
// SCVTF,UCVTF V,V
|
|
// FRINT(AIMNPXZ) V,V
|
|
def : WriteRes<WriteFCvt, [CyUnitV]> {let Latency = 4;}
|
|
|
|
// SCVT/UCVT S/D, Rd = VLD5+V4: 9 cycles.
|
|
def CyWriteCvtToFPR : WriteSequence<[WriteVLD, CyWriteV4]>;
|
|
def : InstRW<[CyWriteCopyToFPR], (instregex "FCVT[AMNPZ][SU][SU][WX][SD]r")>;
|
|
|
|
// FCVT Rd, S/D = V6+LD4: 10 cycles
|
|
def CyWriteCvtToGPR : WriteSequence<[CyWriteV6, WriteLD]>;
|
|
def : InstRW<[CyWriteCvtToGPR], (instregex "[SU]CVTF[SU][WX][SD]r")>;
|
|
|
|
// FCVTL is a WriteV
|
|
|
|
//---
|
|
// 7.9.8-7.9.10 Cryptography, Data Transposition, Table Lookup
|
|
//---
|
|
|
|
def CyWriteCrypto2 : SchedWriteRes<[CyUnitVD]> {let Latency = 2;}
|
|
def : InstRW<[CyWriteCrypto2], (instrs AESIMCrr, AESMCrr, SHA1Hrr,
|
|
AESDrr, AESErr, SHA1SU1rr, SHA256SU0rr,
|
|
SHA1SU0rrr)>;
|
|
|
|
def CyWriteCrypto3 : SchedWriteRes<[CyUnitVD]> {let Latency = 3;}
|
|
def : InstRW<[CyWriteCrypto3], (instrs SHA256SU1rrr)>;
|
|
|
|
def CyWriteCrypto6 : SchedWriteRes<[CyUnitVD]> {let Latency = 6;}
|
|
def : InstRW<[CyWriteCrypto6], (instrs SHA1Crrr, SHA1Mrrr, SHA1Prrr,
|
|
SHA256Hrrr,SHA256H2rrr)>;
|
|
|
|
// TRN,UZP,ZUP are WriteV.
|
|
|
|
// TBL,TBX are WriteV.
|
|
|
|
//---
|
|
// 7.9.11-7.9.14 Load/Store, single element and paired
|
|
//---
|
|
|
|
// Loading into the vector unit takes 5 cycles vs 4 for integer loads.
|
|
def : WriteRes<WriteVLD, [CyUnitLS]> {
|
|
let Latency = 5;
|
|
}
|
|
|
|
// Store-load forwarding is 4 cycles.
|
|
def : WriteRes<WriteVST, [CyUnitLS]> {
|
|
let Latency = 4;
|
|
}
|
|
|
|
// WriteVLDPair/VSTPair sequences are expanded by the target description.
|
|
|
|
//---
|
|
// 7.9.15 Load, element operations
|
|
//---
|
|
|
|
// Only the first WriteVLD and WriteAdr for writeback matches def operands.
|
|
// Subsequent WriteVLDs consume resources. Since all loaded values have the
|
|
// same latency, this is acceptable.
|
|
|
|
// Vd is read 5 cycles after issuing the vector load.
|
|
def : ReadAdvance<ReadVLD, 5>;
|
|
|
|
def : InstRW<[WriteVLD],
|
|
(instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr],
|
|
(instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>;
|
|
|
|
// Register writes from the load's high half are fused micro-ops.
|
|
def : InstRW<[WriteVLD],
|
|
(instregex "LD1Twov(8b|4h|2s|1d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr],
|
|
(instregex "LD1Twov(8b|4h|2s|1d)_POST")>;
|
|
def : InstRW<[WriteVLD, WriteVLD],
|
|
(instregex "LD1Twov(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr, WriteVLD],
|
|
(instregex "LD1Twov(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLD, WriteVLD],
|
|
(instregex "LD1Threev(8b|4h|2s|1d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr, WriteVLD],
|
|
(instregex "LD1Threev(8b|4h|2s|1d)_POST")>;
|
|
def : InstRW<[WriteVLD, WriteVLD, WriteVLD],
|
|
(instregex "LD1Threev(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr, WriteVLD, WriteVLD],
|
|
(instregex "LD1Threev(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLD, WriteVLD],
|
|
(instregex "LD1Fourv(8b|4h|2s|1d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr, WriteVLD],
|
|
(instregex "LD1Fourv(8b|4h|2s|1d)_POST")>;
|
|
def : InstRW<[WriteVLD, WriteVLD, WriteVLD, WriteVLD],
|
|
(instregex "LD1Fourv(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLD, WriteAdr, WriteVLD, WriteVLD, WriteVLD],
|
|
(instregex "LD1Fourv(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD],
|
|
(instregex "LD1i(8|16|32)$")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr],
|
|
(instregex "LD1i(8|16|32)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD], (instrs LD1i64)>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr],(instrs LD1i64_POST)>;
|
|
|
|
def : InstRW<[WriteVLDShuffle],
|
|
(instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr],
|
|
(instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteV],
|
|
(instregex "LD2Twov(8b|4h|2s)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV],
|
|
(instregex "LD2Twov(8b|4h|2s)_POST$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteVLDShuffle],
|
|
(instregex "LD2Twov(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle],
|
|
(instregex "LD2Twov(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV],
|
|
(instregex "LD2i(8|16|32)$")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV],
|
|
(instregex "LD2i(8|16|32)_POST")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV],
|
|
(instregex "LD2i64$")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV],
|
|
(instregex "LD2i64_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteV],
|
|
(instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV],
|
|
(instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV],
|
|
(instregex "LD3Threev(8b|4h|2s)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV],
|
|
(instregex "LD3Threev(8b|4h|2s)_POST")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVLDShuffle],
|
|
(instregex "LD3Threev(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVLDShuffle],
|
|
(instregex "LD3Threev(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV, WriteV],
|
|
(instregex "LD3i(8|16|32)$")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV, WriteV],
|
|
(instregex "LD3i(8|16|32)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteV],
|
|
(instregex "LD3i64$")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteV],
|
|
(instregex "LD3i64_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteV, WriteV],
|
|
(instregex "LD3Rv(8b|4h|2s|16b|8h|4s)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV, WriteV],
|
|
(instregex "LD3Rv(8b|4h|2s|16b|8h|4s)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV],
|
|
(instrs LD3Rv1d,LD3Rv2d)>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV],
|
|
(instrs LD3Rv2d_POST,LD3Rv2d_POST)>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV, WriteV],
|
|
(instregex "LD4Fourv(8b|4h|2s)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV, WriteV],
|
|
(instregex "LD4Fourv(8b|4h|2s)_POST")>;
|
|
def : InstRW<[WriteVLDPairShuffle, WriteVLDPairShuffle,
|
|
WriteVLDPairShuffle, WriteVLDPairShuffle],
|
|
(instregex "LD4Fourv(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteVLDPairShuffle, WriteAdr, WriteVLDPairShuffle,
|
|
WriteVLDPairShuffle, WriteVLDPairShuffle],
|
|
(instregex "LD4Fourv(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV, WriteV, WriteV],
|
|
(instregex "LD4i(8|16|32)$")>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV, WriteV, WriteV],
|
|
(instregex "LD4i(8|16|32)_POST")>;
|
|
|
|
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteV, WriteV],
|
|
(instrs LD4i64)>;
|
|
def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteV],
|
|
(instrs LD4i64_POST)>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteV, WriteV, WriteV],
|
|
(instregex "LD4Rv(8b|4h|2s|16b|8h|4s)$")>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV, WriteV, WriteV],
|
|
(instregex "LD4Rv(8b|4h|2s|16b|8h|4s)_POST")>;
|
|
|
|
def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV, WriteV],
|
|
(instrs LD4Rv1d,LD4Rv2d)>;
|
|
def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV, WriteV],
|
|
(instrs LD4Rv1d_POST,LD4Rv2d_POST)>;
|
|
|
|
//---
|
|
// 7.9.16 Store, element operations
|
|
//---
|
|
|
|
// Only the WriteAdr for writeback matches a def operands.
|
|
// Subsequent WriteVLDs only consume resources.
|
|
|
|
def : InstRW<[WriteVST],
|
|
(instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVST],
|
|
(instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle],
|
|
(instregex "ST1Twov(8b|4h|2s|1d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle],
|
|
(instregex "ST1Twov(8b|4h|2s|1d)_POST")>;
|
|
def : InstRW<[WriteVST, WriteVST],
|
|
(instregex "ST1Twov(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVST, WriteVST],
|
|
(instregex "ST1Twov(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle, WriteVST],
|
|
(instregex "ST1Threev(8b|4h|2s|1d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVST],
|
|
(instregex "ST1Threev(8b|4h|2s|1d)_POST")>;
|
|
def : InstRW<[WriteVST, WriteVST, WriteVST],
|
|
(instregex "ST1Threev(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVST, WriteVST, WriteVST],
|
|
(instregex "ST1Threev(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle, WriteVSTShuffle],
|
|
(instregex "ST1Fourv(8b|4h|2s|1d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],
|
|
(instregex "ST1Fourv(8b|4h|2s|1d)_POST")>;
|
|
def : InstRW<[WriteVST, WriteVST, WriteVST, WriteVST],
|
|
(instregex "ST1Fourv(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVST, WriteVST, WriteVST, WriteVST],
|
|
(instregex "ST1Fourv(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle], (instregex "ST1i(8|16|32)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST1i(8|16|32)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle], (instrs ST1i64)>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle], (instrs ST1i64_POST)>;
|
|
|
|
def : InstRW<[WriteVSTShuffle],
|
|
(instregex "ST2Twov(8b|4h|2s)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle],
|
|
(instregex "ST2Twov(8b|4h|2s)_POST")>;
|
|
def : InstRW<[WriteVSTShuffle, WriteVSTShuffle],
|
|
(instregex "ST2Twov(16b|8h|4s|2d)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],
|
|
(instregex "ST2Twov(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle], (instregex "ST2i(8|16|32)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST2i(8|16|32)_POST")>;
|
|
def : InstRW<[WriteVSTShuffle], (instrs ST2i64)>;
|
|
def : InstRW<[WriteAdr, WriteVSTShuffle], (instrs ST2i64_POST)>;
|
|
|
|
def : InstRW<[WriteVSTShuffle, WriteVSTShuffle],
|
|
(instregex "ST3Threev(8b|4h|2s)$")>;
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def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],
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(instregex "ST3Threev(8b|4h|2s)_POST")>;
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def : InstRW<[WriteVSTShuffle, WriteVSTShuffle, WriteVSTShuffle],
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(instregex "ST3Threev(16b|8h|4s|2d)$")>;
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def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle, WriteVSTShuffle],
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(instregex "ST3Threev(16b|8h|4s|2d)_POST")>;
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|
|
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def : InstRW<[WriteVSTShuffle], (instregex "ST3i(8|16|32)$")>;
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def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST3i(8|16|32)_POST")>;
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|
|
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def :InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST3i64)>;
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def :InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], (instrs ST3i64_POST)>;
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|
|
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def : InstRW<[WriteVSTPairShuffle, WriteVSTPairShuffle],
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|
(instregex "ST4Fourv(8b|4h|2s|1d)$")>;
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|
def : InstRW<[WriteAdr, WriteVSTPairShuffle, WriteVSTPairShuffle],
|
|
(instregex "ST4Fourv(8b|4h|2s|1d)_POST")>;
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|
def : InstRW<[WriteVSTPairShuffle, WriteVSTPairShuffle,
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|
WriteVSTPairShuffle, WriteVSTPairShuffle],
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|
(instregex "ST4Fourv(16b|8h|4s|2d)$")>;
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|
def : InstRW<[WriteAdr, WriteVSTPairShuffle, WriteVSTPairShuffle,
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|
WriteVSTPairShuffle, WriteVSTPairShuffle],
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|
(instregex "ST4Fourv(16b|8h|4s|2d)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTPairShuffle], (instregex "ST4i(8|16|32)$")>;
|
|
def : InstRW<[WriteAdr, WriteVSTPairShuffle], (instregex "ST4i(8|16|32)_POST")>;
|
|
|
|
def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST4i64)>;
|
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def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],(instrs ST4i64_POST)>;
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|
|
|
//---
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|
// Unused SchedRead types
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|
//---
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|
|
|
def : ReadAdvance<ReadI, 0>;
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def : ReadAdvance<ReadISReg, 0>;
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def : ReadAdvance<ReadIEReg, 0>;
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def : ReadAdvance<ReadIM, 0>;
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def : ReadAdvance<ReadIMA, 0>;
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def : ReadAdvance<ReadID, 0>;
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|
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} // SchedModel = CycloneModel
|