449 lines
18 KiB
TableGen
449 lines
18 KiB
TableGen
//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Hexagon Instruction Flags +
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//
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// *** Must match HexagonBaseInfo.h ***
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//===----------------------------------------------------------------------===//
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class IType<bits<5> t> {
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bits<5> Value = t;
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}
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def TypePSEUDO : IType<0>;
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def TypeALU32 : IType<1>;
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def TypeCR : IType<2>;
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def TypeJR : IType<3>;
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def TypeJ : IType<4>;
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def TypeLD : IType<5>;
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def TypeST : IType<6>;
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def TypeSYSTEM : IType<7>;
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def TypeXTYPE : IType<8>;
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def TypeENDLOOP: IType<31>;
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// Maintain list of valid subtargets for each instruction.
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class SubTarget<bits<6> value> {
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bits<6> Value = value;
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}
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def HasAnySubT : SubTarget<0x3f>; // 111111
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def HasV5SubT : SubTarget<0x3e>; // 111110
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def HasV55SubT : SubTarget<0x3c>; // 111100
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def HasV60SubT : SubTarget<0x38>; // 111000
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// Addressing modes for load/store instructions
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class AddrModeType<bits<3> value> {
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bits<3> Value = value;
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}
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def NoAddrMode : AddrModeType<0>; // No addressing mode
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def Absolute : AddrModeType<1>; // Absolute addressing mode
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def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
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def BaseImmOffset : AddrModeType<3>; // Indirect with offset
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def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
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def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
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def PostInc : AddrModeType<6>; // Post increment addressing mode
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class MemAccessSize<bits<4> value> {
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bits<4> Value = value;
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}
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def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
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def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
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def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
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def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
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def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
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def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
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def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
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//===----------------------------------------------------------------------===//
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// Instruction Class Declaration +
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//===----------------------------------------------------------------------===//
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class OpcodeHexagon {
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field bits<32> Inst = ?; // Default to an invalid insn.
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bits<4> IClass = 0; // ICLASS
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let Inst{31-28} = IClass;
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bits<1> zero = 0;
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}
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class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr, InstrItinClass itin, IType type>
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: Instruction {
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let Namespace = "Hexagon";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Constraints = cstr;
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let Itinerary = itin;
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let Size = 4;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<32> SoftFail = 0;
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// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
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// Instruction type according to the ISA.
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IType Type = type;
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let TSFlags{4-0} = Type.Value;
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// Solo instructions, i.e., those that cannot be in a packet with others.
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bits<1> isSolo = 0;
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let TSFlags{5} = isSolo;
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// Packed only with A or X-type instructions.
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bits<1> isSoloAX = 0;
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let TSFlags{6} = isSoloAX;
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// Only A-type instruction in first slot or nothing.
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bits<1> isSoloAin1 = 0;
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let TSFlags{7} = isSoloAin1;
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// Predicated instructions.
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bits<1> isPredicated = 0;
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let TSFlags{8} = isPredicated;
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bits<1> isPredicatedFalse = 0;
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let TSFlags{9} = isPredicatedFalse;
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bits<1> isPredicatedNew = 0;
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let TSFlags{10} = isPredicatedNew;
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bits<1> isPredicateLate = 0;
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let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
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// New-value insn helper fields.
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bits<1> isNewValue = 0;
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let TSFlags{12} = isNewValue; // New-value consumer insn.
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bits<1> hasNewValue = 0;
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let TSFlags{13} = hasNewValue; // New-value producer insn.
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bits<3> opNewValue = 0;
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let TSFlags{16-14} = opNewValue; // New-value produced operand.
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bits<1> isNVStorable = 0;
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let TSFlags{17} = isNVStorable; // Store that can become new-value store.
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bits<1> isNVStore = 0;
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let TSFlags{18} = isNVStore; // New-value store insn.
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bits<1> isCVLoadable = 0;
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let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
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bits<1> isCVLoad = 0;
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let TSFlags{20} = isCVLoad; // Cur-value load insn.
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// Immediate extender helper fields.
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bits<1> isExtendable = 0;
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let TSFlags{21} = isExtendable; // Insn may be extended.
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bits<1> isExtended = 0;
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let TSFlags{22} = isExtended; // Insn must be extended.
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bits<3> opExtendable = 0;
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let TSFlags{25-23} = opExtendable; // Which operand may be extended.
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bits<1> isExtentSigned = 0;
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let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
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bits<5> opExtentBits = 0;
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let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
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bits<2> opExtentAlign = 0;
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let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
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// If an instruction is valid on a subtarget, set the corresponding
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// bit from validSubTargets.
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// By default, instruction is valid on all subtargets.
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SubTarget validSubTargets = HasAnySubT;
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let TSFlags{39-34} = validSubTargets.Value;
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// Addressing mode for load/store instructions.
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AddrModeType addrMode = NoAddrMode;
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let TSFlags{42-40} = addrMode.Value;
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// Memory access size for mem access instructions (load/store)
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MemAccessSize accessSize = NoMemAccess;
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let TSFlags{46-43} = accessSize.Value;
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bits<1> isTaken = 0;
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let TSFlags {47} = isTaken; // Branch prediction.
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bits<1> isFP = 0;
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let TSFlags {48} = isFP; // Floating-point.
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bits<1> hasNewValue2 = 0;
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let TSFlags{50} = hasNewValue2; // Second New-value producer insn.
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bits<3> opNewValue2 = 0;
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let TSFlags{53-51} = opNewValue2; // Second New-value produced operand.
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bits<1> isAccumulator = 0;
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let TSFlags{54} = isAccumulator;
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// Fields used for relation models.
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bit isNonTemporal = 0;
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string isNT = ""; // set to "true" for non-temporal vector stores.
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string BaseOpcode = "";
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string CextOpcode = "";
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string PredSense = "";
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string PNewValue = "";
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string NValueST = ""; // Set to "true" for new-value stores.
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string InputType = ""; // Input is "imm" or "reg" type.
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string isFloat = "false"; // Set to "true" for the floating-point load/store.
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string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
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let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
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"");
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let PNewValue = !if(isPredicatedNew, "new", "");
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let NValueST = !if(isNVStore, "true", "false");
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let isNT = !if(isNonTemporal, "true", "false");
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// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
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}
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//===----------------------------------------------------------------------===//
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// Instruction Classes Definitions +
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//===----------------------------------------------------------------------===//
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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let mayLoad = 1 in
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class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
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let mayLoad = 1 in
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class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: LDInst<outs, ins, asmstr, pattern, cstr>;
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class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: LDInst<outs, ins, asmstr, pattern, cstr>;
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: LDInst<outs, ins, asmstr, pattern, cstr>;
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let mayLoad = 1 in
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class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
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let mayLoad = 1 in
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class LD1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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let mayStore = 1 in
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class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
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class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: STInst<outs, ins, asmstr, pattern, cstr>;
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let mayStore = 1 in
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class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
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// Same as ST0Inst but doesn't derive from OpcodeHexagon.
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let mayStore = 1 in
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class ST1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
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: STInst<outs, ins, asmstr, pattern, cstr, itin>;
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// SYSTEM Instruction Class in V4 can take SLOT0 only
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// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
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class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>,
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OpcodeHexagon;
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// ALU32 Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon;
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// ALU64 Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
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class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
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OpcodeHexagon;
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class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
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: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
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// M Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
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OpcodeHexagon;
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// Same as above but doesn't derive from OpcodeHexagon
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class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
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// M Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
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: MInst<outs, ins, asmstr, pattern, cstr, itin>;
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// S Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
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OpcodeHexagon;
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class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
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// S Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
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: SInst<outs, ins, asmstr, pattern, cstr, itin>;
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// J Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
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// JR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon;
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// CR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>, OpcodeHexagon;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
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OpcodeHexagon;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
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OpcodeHexagon;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr="">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
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OpcodeHexagon;
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//===----------------------------------------------------------------------===//
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// Instruction Classes Definitions -
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//===----------------------------------------------------------------------===//
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//
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// ALU32 patterns
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//.
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class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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//
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// ALU64 patterns.
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//
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class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
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: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
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: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
|
|
|
|
// Post increment ST Instruction.
|
|
class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
|
|
string cstr = "">
|
|
: STInst<outs, ins, asmstr, pattern, cstr>;
|
|
|
|
let mayStore = 1 in
|
|
class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
|
|
string cstr = "">
|
|
: STInst<outs, ins, asmstr, pattern, cstr>;
|
|
|
|
// Post increment LD Instruction.
|
|
class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
|
|
string cstr = "">
|
|
: LDInst<outs, ins, asmstr, pattern, cstr>;
|
|
|
|
let mayLoad = 1 in
|
|
class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
|
|
string cstr = "">
|
|
: LDInst<outs, ins, asmstr, pattern, cstr>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// V4 Instruction Format Definitions +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "HexagonInstrFormatsV4.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// V4 Instruction Format Definitions +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// V60 Instruction Format Definitions +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "HexagonInstrFormatsV60.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// V60 Instruction Format Definitions +
|
|
//===----------------------------------------------------------------------===//
|