103 lines
3.8 KiB
C++
103 lines
3.8 KiB
C++
//===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H
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#define LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H
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#include "PPCInstrInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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/// PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based
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/// hazard recognizer for PPC ooo processors with dispatch-group hazards.
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class PPCDispatchGroupSBHazardRecognizer : public ScoreboardHazardRecognizer {
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const ScheduleDAG *DAG;
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SmallVector<SUnit *, 7> CurGroup;
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unsigned CurSlots, CurBranches;
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bool isLoadAfterStore(SUnit *SU);
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bool isBCTRAfterSet(SUnit *SU);
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bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
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public:
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PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData,
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const ScheduleDAG *DAG_) :
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ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
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CurSlots(0), CurBranches(0) {}
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HazardType getHazardType(SUnit *SU, int Stalls) override;
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bool ShouldPreferAnother(SUnit* SU) override;
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unsigned PreEmitNoops(SUnit *SU) override;
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void EmitInstruction(SUnit *SU) override;
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void AdvanceCycle() override;
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void RecedeCycle() override;
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void Reset() override;
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void EmitNoop() override;
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};
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/// PPCHazardRecognizer970 - This class defines a finite state automata that
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/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
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/// promotes good dispatch group formation and implements noop insertion to
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/// avoid structural hazards that cause significant performance penalties (e.g.
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/// setting the CTR register then branching through it within a dispatch group),
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/// or storing then loading from the same address within a dispatch group.
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class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
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const ScheduleDAG &DAG;
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unsigned NumIssued; // Number of insts issued, including advanced cycles.
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// Various things that can cause a structural hazard.
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// HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
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bool HasCTRSet;
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// StoredPtr - Keep track of the address of any store. If we see a load from
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// the same address (or one that aliases it), disallow the store. We can have
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// up to four stores in one dispatch group, hence we track up to 4.
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//
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// This is null if we haven't seen a store yet. We keep track of both
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// operands of the store here, since we support [r+r] and [r+i] addressing.
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const Value *StoreValue[4];
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int64_t StoreOffset[4];
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uint64_t StoreSize[4];
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unsigned NumStores;
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public:
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PPCHazardRecognizer970(const ScheduleDAG &DAG);
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HazardType getHazardType(SUnit *SU, int Stalls) override;
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void EmitInstruction(SUnit *SU) override;
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void AdvanceCycle() override;
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void Reset() override;
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private:
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/// EndDispatchGroup - Called when we are finishing a new dispatch group.
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///
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void EndDispatchGroup();
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/// GetInstrType - Classify the specified powerpc opcode according to its
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/// pipeline.
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PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
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bool &isFirst, bool &isSingle,bool &isCracked,
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bool &isLoad, bool &isStore);
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bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
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const Value *LoadValue) const;
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};
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} // end namespace llvm
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#endif
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