650 lines
18 KiB
Plaintext
650 lines
18 KiB
Plaintext
//===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
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TODO:
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* lmw/stmw pass a la arm load store optimizer for prolog/epilog
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===-------------------------------------------------------------------------===
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This code:
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unsigned add32carry(unsigned sum, unsigned x) {
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unsigned z = sum + x;
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if (sum + x < x)
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z++;
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return z;
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}
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Should compile to something like:
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addc r3,r3,r4
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addze r3,r3
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instead we get:
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add r3, r4, r3
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cmplw cr7, r3, r4
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mfcr r4 ; 1
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rlwinm r4, r4, 29, 31, 31
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add r3, r3, r4
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Ick.
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===-------------------------------------------------------------------------===
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We compile the hottest inner loop of viterbi to:
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li r6, 0
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b LBB1_84 ;bb432.i
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LBB1_83: ;bb420.i
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lbzx r8, r5, r7
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addi r6, r7, 1
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stbx r8, r4, r7
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LBB1_84: ;bb432.i
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mr r7, r6
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cmplwi cr0, r7, 143
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bne cr0, LBB1_83 ;bb420.i
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The CBE manages to produce:
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li r0, 143
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mtctr r0
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loop:
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lbzx r2, r2, r11
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stbx r0, r2, r9
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addi r2, r2, 1
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bdz later
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b loop
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This could be much better (bdnz instead of bdz) but it still beats us. If we
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produced this with bdnz, the loop would be a single dispatch group.
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===-------------------------------------------------------------------------===
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Lump the constant pool for each function into ONE pic object, and reference
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pieces of it as offsets from the start. For functions like this (contrived
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to have lots of constants obviously):
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double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
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We generate:
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_X:
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lis r2, ha16(.CPI_X_0)
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lfd f0, lo16(.CPI_X_0)(r2)
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lis r2, ha16(.CPI_X_1)
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lfd f2, lo16(.CPI_X_1)(r2)
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fmadd f0, f1, f0, f2
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lis r2, ha16(.CPI_X_2)
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lfd f1, lo16(.CPI_X_2)(r2)
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lis r2, ha16(.CPI_X_3)
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lfd f2, lo16(.CPI_X_3)(r2)
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fmadd f1, f0, f1, f2
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blr
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It would be better to materialize .CPI_X into a register, then use immediates
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off of the register to avoid the lis's. This is even more important in PIC
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mode.
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Note that this (and the static variable version) is discussed here for GCC:
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http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
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Here's another example (the sgn function):
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double testf(double a) {
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return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
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}
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it produces a BB like this:
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LBB1_1: ; cond_true
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lis r2, ha16(LCPI1_0)
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lfs f0, lo16(LCPI1_0)(r2)
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lis r2, ha16(LCPI1_1)
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lis r3, ha16(LCPI1_2)
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lfs f2, lo16(LCPI1_2)(r3)
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lfs f3, lo16(LCPI1_1)(r2)
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fsub f0, f0, f1
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fsel f1, f0, f2, f3
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blr
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===-------------------------------------------------------------------------===
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PIC Code Gen IPO optimization:
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Squish small scalar globals together into a single global struct, allowing the
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address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
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of the GOT on targets with one).
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Note that this is discussed here for GCC:
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http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
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===-------------------------------------------------------------------------===
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Darwin Stub removal:
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We still generate calls to foo$stub, and stubs, on Darwin. This is not
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necessary when building with the Leopard (10.5) or later linker, as stubs are
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generated by ld when necessary. Parameterizing this based on the deployment
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target (-mmacosx-version-min) is probably enough. x86-32 does this right, see
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its logic.
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===-------------------------------------------------------------------------===
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Darwin Stub LICM optimization:
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Loops like this:
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for (...) bar();
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Have to go through an indirect stub if bar is external or linkonce. It would
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be better to compile it as:
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fp = &bar;
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for (...) fp();
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which only computes the address of bar once (instead of each time through the
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stub). This is Darwin specific and would have to be done in the code generator.
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Probably not a win on x86.
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===-------------------------------------------------------------------------===
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Simple IPO for argument passing, change:
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void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
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the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
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of arguments get assigned to r3 through r10. That is, if you have a function
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foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
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argument bytes for r4 and r5. The trick then would be to shuffle the argument
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order for functions we can internalize so that the maximum number of
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integers/pointers get passed in regs before you see any of the fp arguments.
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Instead of implementing this, it would actually probably be easier to just
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implement a PPC fastcc, where we could do whatever we wanted to the CC,
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including having this work sanely.
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===-------------------------------------------------------------------------===
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Fix Darwin FP-In-Integer Registers ABI
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Darwin passes doubles in structures in integer registers, which is very very
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bad. Add something like a BITCAST to LLVM, then do an i-p transformation that
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percolates these things out of functions.
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Check out how horrible this is:
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http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
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This is an extension of "interprocedural CC unmunging" that can't be done with
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just fastcc.
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===-------------------------------------------------------------------------===
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Fold add and sub with constant into non-extern, non-weak addresses so this:
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static int a;
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void bar(int b) { a = b; }
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void foo(unsigned char *c) {
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*c = a;
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}
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So that
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_foo:
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lis r2, ha16(_a)
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la r2, lo16(_a)(r2)
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lbz r2, 3(r2)
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stb r2, 0(r3)
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blr
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Becomes
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_foo:
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lis r2, ha16(_a+3)
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lbz r2, lo16(_a+3)(r2)
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stb r2, 0(r3)
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blr
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===-------------------------------------------------------------------------===
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We should compile these two functions to the same thing:
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#include <stdlib.h>
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void f(int a, int b, int *P) {
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*P = (a-b)>=0?(a-b):(b-a);
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}
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void g(int a, int b, int *P) {
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*P = abs(a-b);
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}
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Further, they should compile to something better than:
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_g:
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subf r2, r4, r3
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subfic r3, r2, 0
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cmpwi cr0, r2, -1
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bgt cr0, LBB2_2 ; entry
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LBB2_1: ; entry
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mr r2, r3
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LBB2_2: ; entry
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stw r2, 0(r5)
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blr
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GCC produces:
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_g:
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subf r4,r4,r3
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srawi r2,r4,31
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xor r0,r2,r4
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subf r0,r2,r0
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stw r0,0(r5)
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blr
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... which is much nicer.
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This theoretically may help improve twolf slightly (used in dimbox.c:142?).
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===-------------------------------------------------------------------------===
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PR5945: This:
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define i32 @clamp0g(i32 %a) {
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entry:
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%cmp = icmp slt i32 %a, 0
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%sel = select i1 %cmp, i32 0, i32 %a
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ret i32 %sel
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}
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Is compile to this with the PowerPC (32-bit) backend:
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_clamp0g:
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cmpwi cr0, r3, 0
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li r2, 0
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blt cr0, LBB1_2
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; BB#1: ; %entry
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mr r2, r3
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LBB1_2: ; %entry
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mr r3, r2
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blr
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This could be reduced to the much simpler:
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_clamp0g:
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srawi r2, r3, 31
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andc r3, r3, r2
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blr
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===-------------------------------------------------------------------------===
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int foo(int N, int ***W, int **TK, int X) {
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int t, i;
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for (t = 0; t < N; ++t)
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for (i = 0; i < 4; ++i)
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W[t / X][i][t % X] = TK[i][t];
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return 5;
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}
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We generate relatively atrocious code for this loop compared to gcc.
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We could also strength reduce the rem and the div:
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http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
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===-------------------------------------------------------------------------===
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We generate ugly code for this:
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void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
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unsigned code = 0;
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if(dx < -dw) code |= 1;
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if(dx > dw) code |= 2;
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if(dy < -dw) code |= 4;
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if(dy > dw) code |= 8;
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if(dz < -dw) code |= 16;
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if(dz > dw) code |= 32;
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*ret = code;
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}
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===-------------------------------------------------------------------------===
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%struct.B = type { i8, [3 x i8] }
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define void @bar(%struct.B* %b) {
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entry:
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%tmp = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
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%tmp = load i32* %tmp ; <uint> [#uses=1]
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%tmp3 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
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%tmp4 = load i32* %tmp3 ; <uint> [#uses=1]
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%tmp8 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=2]
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%tmp9 = load i32* %tmp8 ; <uint> [#uses=1]
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%tmp4.mask17 = shl i32 %tmp4, i8 1 ; <uint> [#uses=1]
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%tmp1415 = and i32 %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
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%tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
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%tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
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%tmp12 = and i32 %tmp9, 2147483647 ; <uint> [#uses=1]
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%tmp13 = or i32 %tmp12, %tmp11 ; <uint> [#uses=1]
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store i32 %tmp13, i32* %tmp8
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ret void
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}
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We emit:
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_foo:
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lwz r2, 0(r3)
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slwi r4, r2, 1
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or r4, r4, r2
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rlwimi r2, r4, 0, 0, 0
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stw r2, 0(r3)
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blr
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We could collapse a bunch of those ORs and ANDs and generate the following
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equivalent code:
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_foo:
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lwz r2, 0(r3)
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rlwinm r4, r2, 1, 0, 0
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or r2, r2, r4
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stw r2, 0(r3)
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blr
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===-------------------------------------------------------------------------===
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Consider a function like this:
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float foo(float X) { return X + 1234.4123f; }
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The FP constant ends up in the constant pool, so we need to get the LR register.
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This ends up producing code like this:
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_foo:
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.LBB_foo_0: ; entry
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mflr r11
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*** stw r11, 8(r1)
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bl "L00000$pb"
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"L00000$pb":
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mflr r2
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addis r2, r2, ha16(.CPI_foo_0-"L00000$pb")
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lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
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fadds f1, f1, f0
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*** lwz r11, 8(r1)
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mtlr r11
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blr
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This is functional, but there is no reason to spill the LR register all the way
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to the stack (the two marked instrs): spilling it to a GPR is quite enough.
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Implementing this will require some codegen improvements. Nate writes:
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"So basically what we need to support the "no stack frame save and restore" is a
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generalization of the LR optimization to "callee-save regs".
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Currently, we have LR marked as a callee-save reg. The register allocator sees
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that it's callee save, and spills it directly to the stack.
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Ideally, something like this would happen:
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LR would be in a separate register class from the GPRs. The class of LR would be
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marked "unspillable". When the register allocator came across an unspillable
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reg, it would ask "what is the best class to copy this into that I *can* spill"
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If it gets a class back, which it will in this case (the gprs), it grabs a free
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register of that class. If it is then later necessary to spill that reg, so be
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it.
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===-------------------------------------------------------------------------===
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We compile this:
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int test(_Bool X) {
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return X ? 524288 : 0;
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}
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to:
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_test:
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cmplwi cr0, r3, 0
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lis r2, 8
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li r3, 0
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beq cr0, LBB1_2 ;entry
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LBB1_1: ;entry
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mr r3, r2
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LBB1_2: ;entry
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blr
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instead of:
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_test:
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addic r2,r3,-1
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subfe r0,r2,r3
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slwi r3,r0,19
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blr
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This sort of thing occurs a lot due to globalopt.
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===-------------------------------------------------------------------------===
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We compile:
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define i32 @bar(i32 %x) nounwind readnone ssp {
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entry:
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%0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
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%neg = sext i1 %0 to i32 ; <i32> [#uses=1]
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ret i32 %neg
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}
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to:
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_bar:
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cntlzw r2, r3
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slwi r2, r2, 26
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srawi r3, r2, 31
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blr
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it would be better to produce:
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_bar:
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addic r3,r3,-1
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subfe r3,r3,r3
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blr
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===-------------------------------------------------------------------------===
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We generate horrible ppc code for this:
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#define N 2000000
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double a[N],c[N];
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void simpleloop() {
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int j;
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for (j=0; j<N; j++)
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c[j] = a[j];
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}
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LBB1_1: ;bb
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lfdx f0, r3, r4
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addi r5, r5, 1 ;; Extra IV for the exit value compare.
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stfdx f0, r2, r4
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addi r4, r4, 8
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xoris r6, r5, 30 ;; This is due to a large immediate.
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cmplwi cr0, r6, 33920
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bne cr0, LBB1_1
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//===---------------------------------------------------------------------===//
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This:
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#include <algorithm>
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inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
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{ return std::make_pair(a + b, a + b < a); }
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bool no_overflow(unsigned a, unsigned b)
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{ return !full_add(a, b).second; }
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Should compile to:
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__Z11no_overflowjj:
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add r4,r3,r4
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subfc r3,r3,r4
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li r3,0
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adde r3,r3,r3
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blr
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(or better) not:
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__Z11no_overflowjj:
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add r2, r4, r3
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cmplw cr7, r2, r3
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mfcr r2
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rlwinm r2, r2, 29, 31, 31
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xori r3, r2, 1
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blr
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//===---------------------------------------------------------------------===//
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We compile some FP comparisons into an mfcr with two rlwinms and an or. For
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example:
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#include <math.h>
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int test(double x, double y) { return islessequal(x, y);}
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int test2(double x, double y) { return islessgreater(x, y);}
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int test3(double x, double y) { return !islessequal(x, y);}
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Compiles into (all three are similar, but the bits differ):
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_test:
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fcmpu cr7, f1, f2
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mfcr r2
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rlwinm r3, r2, 29, 31, 31
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rlwinm r2, r2, 31, 31, 31
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or r3, r2, r3
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blr
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GCC compiles this into:
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_test:
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fcmpu cr7,f1,f2
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cror 30,28,30
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mfcr r3
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rlwinm r3,r3,31,1
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blr
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which is more efficient and can use mfocr. See PR642 for some more context.
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//===---------------------------------------------------------------------===//
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void foo(float *data, float d) {
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long i;
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for (i = 0; i < 8000; i++)
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data[i] = d;
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}
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void foo2(float *data, float d) {
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long i;
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data--;
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for (i = 0; i < 8000; i++) {
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data[1] = d;
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data++;
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}
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}
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These compile to:
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_foo:
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li r2, 0
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LBB1_1: ; bb
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addi r4, r2, 4
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stfsx f1, r3, r2
|
|
cmplwi cr0, r4, 32000
|
|
mr r2, r4
|
|
bne cr0, LBB1_1 ; bb
|
|
blr
|
|
_foo2:
|
|
li r2, 0
|
|
LBB2_1: ; bb
|
|
addi r4, r2, 4
|
|
stfsx f1, r3, r2
|
|
cmplwi cr0, r4, 32000
|
|
mr r2, r4
|
|
bne cr0, LBB2_1 ; bb
|
|
blr
|
|
|
|
The 'mr' could be eliminated to folding the add into the cmp better.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
Codegen for the following (low-probability) case deteriorated considerably
|
|
when the correctness fixes for unordered comparisons went in (PR 642, 58871).
|
|
It should be possible to recover the code quality described in the comments.
|
|
|
|
; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3
|
|
; This should produce one 'or' or 'cror' instruction per function.
|
|
|
|
; RUN: llvm-as < %s | llc -march=ppc32 | grep mfcr | count 3
|
|
; PR2964
|
|
|
|
define i32 @test(double %x, double %y) nounwind {
|
|
entry:
|
|
%tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1]
|
|
%tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp345
|
|
}
|
|
|
|
define i32 @test2(double %x, double %y) nounwind {
|
|
entry:
|
|
%tmp3 = fcmp one double %x, %y ; <i1> [#uses=1]
|
|
%tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp345
|
|
}
|
|
|
|
define i32 @test3(double %x, double %y) nounwind {
|
|
entry:
|
|
%tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1]
|
|
%tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp34
|
|
}
|
|
//===----------------------------------------------------------------------===//
|
|
; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
|
|
|
|
; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
|
|
; should not be generated except with -enable-finite-only-fp-math or the like).
|
|
; With the correctness fixes for PR642 (58871) LowerSELECT_CC would need to
|
|
; recognize a more elaborate tree than a simple SETxx.
|
|
|
|
define double @test_FNEG_sel(double %A, double %B, double %C) {
|
|
%D = fsub double -0.000000e+00, %A ; <double> [#uses=1]
|
|
%Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1]
|
|
%E = select i1 %Cond, double %B, double %C ; <double> [#uses=1]
|
|
ret double %E
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
The save/restore sequence for CR in prolog/epilog is terrible:
|
|
- Each CR subreg is saved individually, rather than doing one save as a unit.
|
|
- On Darwin, the save is done after the decrement of SP, which means the offset
|
|
from SP of the save slot can be too big for a store instruction, which means we
|
|
need an additional register (currently hacked in 96015+96020; the solution there
|
|
is correct, but poor).
|
|
- On SVR4 the same thing can happen, and I don't think saving before the SP
|
|
decrement is safe on that target, as there is no red zone. This is currently
|
|
broken AFAIK, although it's not a target I can exercise.
|
|
The following demonstrates the problem:
|
|
extern void bar(char *p);
|
|
void foo() {
|
|
char x[100000];
|
|
bar(x);
|
|
__asm__("" ::: "cr2");
|
|
}
|
|
|
|
//===-------------------------------------------------------------------------===
|
|
Naming convention for instruction formats is very haphazard.
|
|
We have agreed on a naming scheme as follows:
|
|
|
|
<INST_form>{_<OP_type><OP_len>}+
|
|
|
|
Where:
|
|
INST_form is the instruction format (X-form, etc.)
|
|
OP_type is the operand type - one of OPC (opcode), RD (register destination),
|
|
RS (register source),
|
|
RDp (destination register pair),
|
|
RSp (source register pair), IM (immediate),
|
|
XO (extended opcode)
|
|
OP_len is the length of the operand in bits
|
|
|
|
VSX register operands would be of length 6 (split across two fields),
|
|
condition register fields of length 3.
|
|
We would not need denote reserved fields in names of instruction formats.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
Instruction fusion was introduced in ISA 2.06 and more opportunities added in
|
|
ISA 2.07. LLVM needs to add infrastructure to recognize fusion opportunities
|
|
and force instruction pairs to be scheduled together.
|
|
|