49 lines
2.7 KiB
LLVM
49 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
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; R600 supports 8 fetches in a clause
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; CHECK: {{^}}fetch_limits_r600:
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; CHECK: Fetch clause
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; CHECK: Fetch clause
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define void @fetch_limits_r600() #0 {
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entry:
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%0 = load <4 x float>, <4 x float> addrspace(8)* null
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%1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
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%2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
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%3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
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%4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
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%5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
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%6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
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%7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
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%8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
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%res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
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%res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
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%res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
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%res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
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%res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
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%res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
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%res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
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%res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
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%res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
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%a = fadd <4 x float> %res0, %res1
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%b = fadd <4 x float> %res2, %res3
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%c = fadd <4 x float> %res4, %res5
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%d = fadd <4 x float> %res6, %res7
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%e = fadd <4 x float> %res8, %a
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%bc = fadd <4 x float> %b, %c
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%de = fadd <4 x float> %d, %e
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%bcde = fadd <4 x float> %bc, %de
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call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1)
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ret void
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}
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attributes #0 = { "ShaderType"="0" } ; Pixel Shader
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declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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