32 lines
1.1 KiB
LLVM
32 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s \
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; RUN: | FileCheck %s -check-prefix CHECK-SMALL-CODE
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; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -code-model=large -o - %s \
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; RUN: | FileCheck %s -check-prefix CHECK-LARGE-CODE
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; RUN: llc -mtriple=thumbv7-windows-msvc -mcpu=cortex-a9 -o - %s \
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; RUN: | FileCheck %s -check-prefix CHECK-MSVC
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define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) {
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entry:
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%vla = alloca i8, i32 %sz, align 1
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%arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx
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%0 = load volatile i8, i8* %arrayidx, align 1
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ret i8 %0
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}
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; CHECK-SMALL-CODE: adds [[R4:r[0-9]+]], #7
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; CHECK-SMALL-CODE: bic [[R4]], [[R4]], #7
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; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2
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; CHECK-SMALL-CODE: bl __chkstk
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; CHECK-SMALL-CODE: sub.w sp, sp, r4
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; CHECK-LARGE-CODE: adds [[R4:r[0-9]+]], #7
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; CHECK-LARGE-CODE: bic [[R4]], [[R4]], #7
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; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2
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; CHECK-LARGE-CODE: movw [[IP:r[0-9]+]], :lower16:__chkstk
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; CHECK-LARGE-CODE: movt [[IP]], :upper16:__chkstk
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; CHECK-LARGE-CODE: blx [[IP]]
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; CHECK-LARGE-CODE: sub.w sp, sp, r4
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; CHECK-MSVC-NOT: __chkstk
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