35 lines
1.5 KiB
LLVM
35 lines
1.5 KiB
LLVM
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
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; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
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; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
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; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
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; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
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; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
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; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
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; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
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; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
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; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
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define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
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entry:
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%tmp1 = zext i64 %AL to i128
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%tmp23 = zext i64 %AH to i128
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%tmp4 = shl i128 %tmp23, 64
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%tmp5 = or i128 %tmp4, %tmp1
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%tmp67 = zext i64 %BL to i128
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%tmp89 = zext i64 %BH to i128
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%tmp11 = shl i128 %tmp89, 64
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%tmp12 = or i128 %tmp11, %tmp67
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%tmp15 = add i128 %tmp12, %tmp5
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%tmp1617 = trunc i128 %tmp15 to i64
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store i64 %tmp1617, i64* %RL
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%tmp21 = lshr i128 %tmp15, 64
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%tmp2122 = trunc i128 %tmp21 to i64
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store i64 %tmp2122, i64* %RH
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ret void
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}
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