211 lines
7.2 KiB
LLVM
211 lines
7.2 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@c = global i32 4, align 4
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@d = global i32 9, align 4
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@uc = global i32 4, align 4
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@ud = global i32 9, align 4
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@b1 = common global i32 0, align 4
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; Function Attrs: nounwind
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define void @eq() {
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entry:
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; CHECK-LABEL: .ent eq
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%cmp = icmp eq i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
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; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
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; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
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; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
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; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @ne() {
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entry:
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; CHECK-LABEL: .ent ne
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%cmp = icmp ne i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
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; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
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; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
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; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
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; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @ugt() {
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entry:
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; CHECK-LABEL: .ent ugt
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%0 = load i32, i32* @uc, align 4
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%1 = load i32, i32* @ud, align 4
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%cmp = icmp ugt i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
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; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
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; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
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; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @ult() {
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entry:
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; CHECK-LABEL: .ent ult
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%0 = load i32, i32* @uc, align 4
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%1 = load i32, i32* @ud, align 4
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%cmp = icmp ult i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
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; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
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; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
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; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @uge() {
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entry:
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; CHECK-LABEL: .ent uge
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%0 = load i32, i32* @uc, align 4
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%1 = load i32, i32* @ud, align 4
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%cmp = icmp uge i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
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; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
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; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
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; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
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; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @ule() {
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entry:
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; CHECK-LABEL: .ent ule
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%0 = load i32, i32* @uc, align 4
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%1 = load i32, i32* @ud, align 4
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%cmp = icmp ule i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
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; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
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; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
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; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
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; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @sgt() {
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entry:
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; CHECK-LABEL: .ent sgt
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%cmp = icmp sgt i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
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; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
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; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
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; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @slt() {
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entry:
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; CHECK-LABEL: .ent slt
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%cmp = icmp slt i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
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; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
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; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
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; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @sge() {
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entry:
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; CHECK-LABEL: .ent sge
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%cmp = icmp sge i32 %0, %1
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
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; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
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; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
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; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
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; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
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ret void
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}
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; Function Attrs: nounwind
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define void @sle() {
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entry:
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; CHECK-LABEL: .ent sle
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%cmp = icmp sle i32 %0, %1
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%conv = zext i1 %cmp to i32
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; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
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; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
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; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
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; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
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; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
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; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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