186 lines
4.5 KiB
LLVM
186 lines
4.5 KiB
LLVM
; RUN: llc -march=mipsel -O0 < %s | FileCheck %s -check-prefix=None
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=Default
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; RUN: llc -march=mipsel -O1 -relocation-model=static < %s | \
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; RUN: FileCheck %s -check-prefix=STATICO1
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; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD
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; RUN: llc -march=mipsel -disable-mips-df-backward-search \
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; RUN: -disable-mips-df-succbb-search=false < %s | \
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; RUN: FileCheck %s -check-prefix=SUCCBB
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define void @foo1() nounwind {
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entry:
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; Default: jalr
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; Default-NOT: nop
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; Default: jr
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; Default-NOT: nop
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; Default: .end
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; None: jalr
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; None: nop
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; None: jr
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; None: nop
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; None: .end
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tail call void @foo2(i32 3) nounwind
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ret void
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}
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declare void @foo2(i32)
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; Check that cvt.d.w goes into jalr's delay slot.
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;
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define void @foo3(i32 %a) nounwind {
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entry:
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; Default-LABEL: foo3:
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; Default: jalr
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; Default: cvt.d.w
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%conv = sitofp i32 %a to double
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tail call void @foo4(double %conv) nounwind
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ret void
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}
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declare void @foo4(double)
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@g2 = external global i32
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@g1 = external global i32
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@g3 = external global i32
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; Check that branch delay slot can be filled with an instruction with operand
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; $1.
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;
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; Default-LABEL: foo5:
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; Default-NOT: nop
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define void @foo5(i32 %a) nounwind {
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entry:
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%0 = load i32, i32* @g2, align 4
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%tobool = icmp eq i32 %a, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then:
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%1 = load i32, i32* @g1, align 4
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%add = add nsw i32 %1, %0
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store i32 %add, i32* @g1, align 4
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br label %if.end
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if.else:
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%2 = load i32, i32* @g3, align 4
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%sub = sub nsw i32 %2, %0
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store i32 %sub, i32* @g3, align 4
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br label %if.end
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if.end:
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ret void
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}
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; Check that delay slot filler can place mov.s or mov.d in delay slot.
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;
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; Default-LABEL: foo6:
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; Default-NOT: nop
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; Default: .end foo6
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define void @foo6(float %a0, double %a1) nounwind {
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entry:
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tail call void @foo7(double %a1, float %a0) nounwind
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ret void
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}
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declare void @foo7(double, float)
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; Check that a store can move past other memory instructions.
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;
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; STATICO1-LABEL: foo8:
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; STATICO1: jalr ${{[0-9]+}}
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; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
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@foo9 = common global void ()* null, align 4
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define i32 @foo8(i32 %a) nounwind {
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entry:
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store i32 %a, i32* @g1, align 4
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%0 = load void ()*, void ()** @foo9, align 4
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tail call void %0() nounwind
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%1 = load i32, i32* @g1, align 4
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%add = add nsw i32 %1, %a
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ret i32 %add
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}
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; Test searchForward. Check that the second jal's slot is filled with another
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; instruction in the same block.
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;
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; FORWARD-LABEL: foo10:
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; FORWARD: jal foo11
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; FORWARD: jal foo11
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; FORWARD-NOT: nop
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; FORWARD: end foo10
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define void @foo10() nounwind {
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entry:
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tail call void @foo11() nounwind
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tail call void @foo11() nounwind
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store i32 0, i32* @g1, align 4
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tail call void @foo11() nounwind
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store i32 0, i32* @g1, align 4
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ret void
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}
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declare void @foo11()
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; Check that delay slots of branches in both the entry block and loop body are
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; filled.
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;
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; SUCCBB-LABEL: succbbs_loop1:
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; SUCCBB: blez $5, $BB
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; SUCCBB-NEXT: addiu
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; SUCCBB: bnez ${{[0-9]+}}, $BB
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; SUCCBB-NEXT: addiu
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define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) {
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entry:
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%cmp4 = icmp sgt i32 %n, 0
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br i1 %cmp4, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%s.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.05
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%0 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %0, %s.06
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%inc = add nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%s.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
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ret i32 %s.0.lcssa
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}
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; Check that the first branch has its slot filled.
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;
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; SUCCBB-LABEL: succbbs_br1:
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; SUCCBB: beqz ${{[0-9]+}}, $BB
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; SUCCBB-NEXT: lw ${{[0-9]+}}, %got(foo101)(${{[0-9]+}})
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define internal fastcc void @foo101() {
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entry:
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tail call void @foo100()
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tail call void @foo100()
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ret void
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}
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define void @succbbs_br1(i32 %a) {
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entry:
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%tobool = icmp eq i32 %a, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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tail call fastcc void @foo101()
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br label %if.end
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if.end: ; preds = %entry, %if.then
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ret void
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}
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declare void @foo100()
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