537 lines
19 KiB
C++
537 lines
19 KiB
C++
//===-- SILoadStoreOptimizer.cpp ------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass tries to fuse DS instructions with close by immediate offsets.
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// This will fuse operations such as
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// ds_read_b32 v0, v2 offset:16
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// ds_read_b32 v1, v2 offset:32
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// ==>
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// ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
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//
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//
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// Future improvements:
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//
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// - This currently relies on the scheduler to place loads and stores next to
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// each other, and then only merges adjacent pairs of instructions. It would
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// be good to be more flexible with interleaved instructions, and possibly run
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// before scheduling. It currently missing stores of constants because loading
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// the constant into the data register is placed between the stores, although
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// this is arguably a scheduling problem.
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//
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// - Live interval recomputing seems inefficient. This currently only matches
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// one pair, and recomputes live intervals and moves on to the next pair. It
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// would be better to compute a list of all merges that need to occur.
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//
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// - With a list of instructions to process, we can also merge more. If a
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// cluster of loads have offsets that are too large to fit in the 8-bit
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// offsets, but are close enough to fit in the 8 bits, we can add to the base
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// pointer and use the new reduced offsets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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#include <iterator>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "si-load-store-opt"
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namespace {
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class SILoadStoreOptimizer : public MachineFunctionPass {
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private:
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const SIInstrInfo *TII = nullptr;
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const SIRegisterInfo *TRI = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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AliasAnalysis *AA = nullptr;
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static bool offsetsCanBeCombined(unsigned Offset0,
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unsigned Offset1,
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unsigned EltSize);
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MachineBasicBlock::iterator findMatchingDSInst(
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MachineBasicBlock::iterator I,
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unsigned EltSize,
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SmallVectorImpl<MachineInstr*> &InstsToMove);
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MachineBasicBlock::iterator mergeRead2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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ArrayRef<MachineInstr*> InstsToMove);
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MachineBasicBlock::iterator mergeWrite2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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ArrayRef<MachineInstr*> InstsToMove);
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public:
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static char ID;
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SILoadStoreOptimizer() : MachineFunctionPass(ID) {}
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SILoadStoreOptimizer(const TargetMachine &TM_) : MachineFunctionPass(ID) {
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initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
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}
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bool optimizeBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Load / Store Optimizer"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<AAResultsWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // end anonymous namespace.
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INITIALIZE_PASS_BEGIN(SILoadStoreOptimizer, DEBUG_TYPE,
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"SI Load / Store Optimizer", false, false)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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INITIALIZE_PASS_END(SILoadStoreOptimizer, DEBUG_TYPE,
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"SI Load / Store Optimizer", false, false)
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char SILoadStoreOptimizer::ID = 0;
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char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
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FunctionPass *llvm::createSILoadStoreOptimizerPass(TargetMachine &TM) {
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return new SILoadStoreOptimizer(TM);
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}
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static void moveInstsAfter(MachineBasicBlock::iterator I,
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ArrayRef<MachineInstr*> InstsToMove) {
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MachineBasicBlock *MBB = I->getParent();
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++I;
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for (MachineInstr *MI : InstsToMove) {
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MI->removeFromParent();
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MBB->insert(I, MI);
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}
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}
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static void addDefsToList(const MachineInstr &MI,
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SmallVectorImpl<const MachineOperand *> &Defs) {
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for (const MachineOperand &Def : MI.defs()) {
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Defs.push_back(&Def);
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}
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}
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static bool memAccessesCanBeReordered(MachineBasicBlock::iterator A,
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MachineBasicBlock::iterator B,
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const SIInstrInfo *TII,
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AliasAnalysis * AA) {
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return (TII->areMemAccessesTriviallyDisjoint(*A, *B, AA) ||
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// RAW or WAR - cannot reorder
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// WAW - cannot reorder
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// RAR - safe to reorder
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!(A->mayStore() || B->mayStore()));
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}
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// Add MI and its defs to the lists if MI reads one of the defs that are
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// already in the list. Returns true in that case.
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static bool
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addToListsIfDependent(MachineInstr &MI,
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SmallVectorImpl<const MachineOperand *> &Defs,
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SmallVectorImpl<MachineInstr*> &Insts) {
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for (const MachineOperand *Def : Defs) {
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bool ReadDef = MI.readsVirtualRegister(Def->getReg());
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// If ReadDef is true, then there is a use of Def between I
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// and the instruction that I will potentially be merged with. We
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// will need to move this instruction after the merged instructions.
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if (ReadDef) {
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Insts.push_back(&MI);
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addDefsToList(MI, Defs);
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return true;
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}
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}
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return false;
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}
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static bool
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canMoveInstsAcrossMemOp(MachineInstr &MemOp,
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ArrayRef<MachineInstr*> InstsToMove,
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const SIInstrInfo *TII,
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AliasAnalysis *AA) {
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assert(MemOp.mayLoadOrStore());
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for (MachineInstr *InstToMove : InstsToMove) {
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if (!InstToMove->mayLoadOrStore())
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continue;
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if (!memAccessesCanBeReordered(MemOp, *InstToMove, TII, AA))
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return false;
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}
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return true;
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}
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bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0,
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unsigned Offset1,
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unsigned Size) {
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// XXX - Would the same offset be OK? Is there any reason this would happen or
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// be useful?
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if (Offset0 == Offset1)
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return false;
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// This won't be valid if the offset isn't aligned.
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if ((Offset0 % Size != 0) || (Offset1 % Size != 0))
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return false;
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unsigned EltOffset0 = Offset0 / Size;
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unsigned EltOffset1 = Offset1 / Size;
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// Check if the new offsets fit in the reduced 8-bit range.
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if (isUInt<8>(EltOffset0) && isUInt<8>(EltOffset1))
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return true;
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// If the offset in elements doesn't fit in 8-bits, we might be able to use
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// the stride 64 versions.
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if ((EltOffset0 % 64 != 0) || (EltOffset1 % 64) != 0)
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return false;
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return isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64);
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}
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MachineBasicBlock::iterator
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SILoadStoreOptimizer::findMatchingDSInst(MachineBasicBlock::iterator I,
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unsigned EltSize,
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SmallVectorImpl<MachineInstr*> &InstsToMove) {
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator MBBI = I;
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++MBBI;
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SmallVector<const MachineOperand *, 8> DefsToMove;
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addDefsToList(*I, DefsToMove);
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for ( ; MBBI != E; ++MBBI) {
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if (MBBI->getOpcode() != I->getOpcode()) {
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// This is not a matching DS instruction, but we can keep looking as
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// long as one of these conditions are met:
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// 1. It is safe to move I down past MBBI.
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// 2. It is safe to move MBBI down past the instruction that I will
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// be merged into.
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if (MBBI->hasUnmodeledSideEffects())
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// We can't re-order this instruction with respect to other memory
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// opeations, so we fail both conditions mentioned above.
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return E;
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if (MBBI->mayLoadOrStore() &&
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!memAccessesCanBeReordered(*I, *MBBI, TII, AA)) {
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// We fail condition #1, but we may still be able to satisfy condition
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// #2. Add this instruction to the move list and then we will check
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// if condition #2 holds once we have selected the matching instruction.
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InstsToMove.push_back(&*MBBI);
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addDefsToList(*MBBI, DefsToMove);
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continue;
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}
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// When we match I with another DS instruction we will be moving I down
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// to the location of the matched instruction any uses of I will need to
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// be moved down as well.
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addToListsIfDependent(*MBBI, DefsToMove, InstsToMove);
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continue;
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}
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// Don't merge volatiles.
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if (MBBI->hasOrderedMemoryRef())
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return E;
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// Handle a case like
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// DS_WRITE_B32 addr, v, idx0
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// w = DS_READ_B32 addr, idx0
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// DS_WRITE_B32 addr, f(w), idx1
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// where the DS_READ_B32 ends up in InstsToMove and therefore prevents
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// merging of the two writes.
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if (addToListsIfDependent(*MBBI, DefsToMove, InstsToMove))
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continue;
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int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
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const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
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const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
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// Check same base pointer. Be careful of subregisters, which can occur with
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// vectors of pointers.
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if (AddrReg0.getReg() == AddrReg1.getReg() &&
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AddrReg0.getSubReg() == AddrReg1.getSubReg()) {
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int OffsetIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(),
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AMDGPU::OpName::offset);
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unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff;
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unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm() & 0xffff;
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// Check both offsets fit in the reduced range.
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// We also need to go through the list of instructions that we plan to
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// move and make sure they are all safe to move down past the merged
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// instruction.
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if (offsetsCanBeCombined(Offset0, Offset1, EltSize) &&
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canMoveInstsAcrossMemOp(*MBBI, InstsToMove, TII, AA))
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return MBBI;
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}
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// We've found a load/store that we couldn't merge for some reason.
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// We could potentially keep looking, but we'd need to make sure that
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// it was safe to move I and also all the instruction in InstsToMove
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// down past this instruction.
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if (!memAccessesCanBeReordered(*I, *MBBI, TII, AA) || // check if we can move I across MBBI
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!canMoveInstsAcrossMemOp(*MBBI, InstsToMove, TII, AA) // check if we can move all I's users
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)
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break;
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}
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return E;
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}
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MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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ArrayRef<MachineInstr*> InstsToMove) {
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MachineBasicBlock *MBB = I->getParent();
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// Be careful, since the addresses could be subregisters themselves in weird
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// cases, like vectors of pointers.
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const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
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const MachineOperand *Dest0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst);
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const MachineOperand *Dest1 = TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst);
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unsigned Offset0
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= TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
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unsigned Offset1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff;
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unsigned NewOffset0 = Offset0 / EltSize;
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unsigned NewOffset1 = Offset1 / EltSize;
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unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64;
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// Prefer the st64 form if we can use it, even if we can fit the offset in the
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// non st64 version. I'm not sure if there's any real reason to do this.
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bool UseST64 = (NewOffset0 % 64 == 0) && (NewOffset1 % 64 == 0);
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if (UseST64) {
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NewOffset0 /= 64;
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NewOffset1 /= 64;
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Opc = (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64;
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}
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unsigned SubRegIdx0 = (EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
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unsigned SubRegIdx1 = (EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3;
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if (NewOffset0 > NewOffset1) {
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// Canonicalize the merged instruction so the smaller offset comes first.
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std::swap(NewOffset0, NewOffset1);
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std::swap(SubRegIdx0, SubRegIdx1);
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}
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assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
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(NewOffset0 != NewOffset1) &&
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"Computed offset doesn't fit");
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const MCInstrDesc &Read2Desc = TII->get(Opc);
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const TargetRegisterClass *SuperRC
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= (EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass;
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unsigned DestReg = MRI->createVirtualRegister(SuperRC);
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DebugLoc DL = I->getDebugLoc();
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MachineInstrBuilder Read2 = BuildMI(*MBB, Paired, DL, Read2Desc, DestReg)
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.add(*AddrReg) // addr
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset1) // offset1
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.addImm(0) // gds
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.addMemOperand(*I->memoperands_begin())
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.addMemOperand(*Paired->memoperands_begin());
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(void)Read2;
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const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
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// Copy to the old destination registers.
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BuildMI(*MBB, Paired, DL, CopyDesc)
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.add(*Dest0) // Copy to same destination including flags and sub reg.
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.addReg(DestReg, 0, SubRegIdx0);
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MachineInstr *Copy1 = BuildMI(*MBB, Paired, DL, CopyDesc)
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.add(*Dest1)
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.addReg(DestReg, RegState::Kill, SubRegIdx1);
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moveInstsAfter(Copy1, InstsToMove);
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MachineBasicBlock::iterator Next = std::next(I);
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I->eraseFromParent();
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Paired->eraseFromParent();
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DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');
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return Next;
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}
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MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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ArrayRef<MachineInstr*> InstsToMove) {
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MachineBasicBlock *MBB = I->getParent();
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// Be sure to use .addOperand(), and not .addReg() with these. We want to be
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// sure we preserve the subregister index and any register flags set on them.
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const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
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const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0);
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const MachineOperand *Data1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::data0);
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unsigned Offset0
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= TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
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unsigned Offset1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff;
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unsigned NewOffset0 = Offset0 / EltSize;
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unsigned NewOffset1 = Offset1 / EltSize;
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unsigned Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64;
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// Prefer the st64 form if we can use it, even if we can fit the offset in the
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// non st64 version. I'm not sure if there's any real reason to do this.
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bool UseST64 = (NewOffset0 % 64 == 0) && (NewOffset1 % 64 == 0);
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if (UseST64) {
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NewOffset0 /= 64;
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NewOffset1 /= 64;
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Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 : AMDGPU::DS_WRITE2ST64_B64;
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}
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if (NewOffset0 > NewOffset1) {
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// Canonicalize the merged instruction so the smaller offset comes first.
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std::swap(NewOffset0, NewOffset1);
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std::swap(Data0, Data1);
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}
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assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
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(NewOffset0 != NewOffset1) &&
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"Computed offset doesn't fit");
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const MCInstrDesc &Write2Desc = TII->get(Opc);
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DebugLoc DL = I->getDebugLoc();
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MachineInstrBuilder Write2 = BuildMI(*MBB, Paired, DL, Write2Desc)
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.add(*Addr) // addr
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.add(*Data0) // data0
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.add(*Data1) // data1
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset1) // offset1
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.addImm(0) // gds
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.addMemOperand(*I->memoperands_begin())
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.addMemOperand(*Paired->memoperands_begin());
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moveInstsAfter(Write2, InstsToMove);
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MachineBasicBlock::iterator Next = std::next(I);
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I->eraseFromParent();
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Paired->eraseFromParent();
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DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n');
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return Next;
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}
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// Scan through looking for adjacent LDS operations with constant offsets from
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// the same base register. We rely on the scheduler to do the hard work of
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// clustering nearby loads, and assume these are all adjacent.
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bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
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bool Modified = false;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
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MachineInstr &MI = *I;
|
|
|
|
// Don't combine if volatile.
|
|
if (MI.hasOrderedMemoryRef()) {
|
|
++I;
|
|
continue;
|
|
}
|
|
|
|
SmallVector<MachineInstr*, 8> InstsToMove;
|
|
unsigned Opc = MI.getOpcode();
|
|
if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
|
|
unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4;
|
|
MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size,
|
|
InstsToMove);
|
|
if (Match != E) {
|
|
Modified = true;
|
|
I = mergeRead2Pair(I, Match, Size, InstsToMove);
|
|
} else {
|
|
++I;
|
|
}
|
|
|
|
continue;
|
|
} else if (Opc == AMDGPU::DS_WRITE_B32 || Opc == AMDGPU::DS_WRITE_B64) {
|
|
unsigned Size = (Opc == AMDGPU::DS_WRITE_B64) ? 8 : 4;
|
|
MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size,
|
|
InstsToMove);
|
|
if (Match != E) {
|
|
Modified = true;
|
|
I = mergeWrite2Pair(I, Match, Size, InstsToMove);
|
|
} else {
|
|
++I;
|
|
}
|
|
|
|
continue;
|
|
}
|
|
|
|
++I;
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
|
if (skipFunction(*MF.getFunction()))
|
|
return false;
|
|
|
|
const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
|
|
if (!STM.loadStoreOptEnabled())
|
|
return false;
|
|
|
|
TII = STM.getInstrInfo();
|
|
TRI = &TII->getRegisterInfo();
|
|
|
|
MRI = &MF.getRegInfo();
|
|
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
|
|
|
|
DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
|
|
|
|
bool Modified = false;
|
|
|
|
for (MachineBasicBlock &MBB : MF)
|
|
Modified |= optimizeBlock(MBB);
|
|
|
|
return Modified;
|
|
}
|