178 lines
6.5 KiB
C++
178 lines
6.5 KiB
C++
//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMachineFunction.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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// FIXME: Maybe this should be on by default when Mips16 is specified
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//
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static cl::opt<bool>
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Mixed16_32("mips-mixed-16-32", cl::init(false),
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cl::desc("Allow for a mixture of Mips16 "
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"and Mips32 code in a single output file"),
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cl::Hidden);
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static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
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cl::desc("Compile all functions that don't use "
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"floating point as Mips 16"),
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cl::Hidden);
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static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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cl::desc("Enable mips16 hard float."),
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cl::init(false));
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static cl::opt<bool>
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Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
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cl::desc("Enable mips16 constant islands."),
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cl::init(true));
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static cl::opt<bool>
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GPOpt("mgpopt", cl::Hidden,
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cl::desc("Enable gp-relative addressing of mips small data items"));
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void MipsSubtarget::anchor() { }
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MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, bool little,
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const MipsTargetMachine &TM)
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
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IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
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NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
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IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
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HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
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Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
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HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(),
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InstrInfo(
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MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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FrameLowering(MipsFrameLowering::create(*this)),
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TLInfo(MipsTargetLowering::create(TM, *this)) {
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PreviousInMips16Mode = InMips16Mode;
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if (MipsArchVersion == MipsDefault)
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MipsArchVersion = Mips32;
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// Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
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// been tested and currently exist for the integrated assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips5)
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report_fatal_error("Code generation for MIPS-V is not implemented", false);
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// Check if Architecture and ABI are compatible.
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assert(((!isGP64bit() && isABI_O32()) ||
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(isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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"Invalid Arch & ABI pair.");
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if (hasMSA() && !isFP64bit())
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report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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"See -mattr=+fp64.",
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false);
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if (!isABI_O32() && !useOddSPReg())
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report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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if (IsFPXX && (isABI_N32() || isABI_N64()))
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report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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if (hasMips32r6()) {
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StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
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assert(isFP64bit());
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assert(isNaN2008());
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if (hasDSP())
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report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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}
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if (NoABICalls && TM.isPositionIndependent())
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report_fatal_error("position-independent code requires '-mabicalls'");
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if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
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NoABICalls = true;
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// Set UseSmallSection.
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UseSmallSection = GPOpt;
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if (!NoABICalls && GPOpt) {
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errs() << "warning: cannot use small-data accesses for '-mabicalls'"
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<< "\n";
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UseSmallSection = false;
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}
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}
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bool MipsSubtarget::isPositionIndependent() const {
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return TM.isPositionIndependent();
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}
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/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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bool MipsSubtarget::enablePostRAScheduler() const { return true; }
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void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(isGP64bit() ?
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&Mips::GPR64RegClass : &Mips::GPR32RegClass);
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}
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CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
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return CodeGenOpt::Aggressive;
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}
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MipsSubtarget &
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MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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const TargetMachine &TM) {
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std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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if (InMips16Mode && !IsSoftFloat)
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InMips16HardFloat = true;
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return *this;
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}
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bool MipsSubtarget::useConstantIslands() {
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DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
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return Mips16ConstantIslands;
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}
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Reloc::Model MipsSubtarget::getRelocationModel() const {
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return TM.getRelocationModel();
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}
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bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
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bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
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bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
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const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
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