393 lines
15 KiB
C++
393 lines
15 KiB
C++
//===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===---------------------------------------------------------------------===//
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//
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// This pass performs peephole optimizations to clean up ugly code
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// sequences at the MachineInstruction layer. It runs at the end of
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// the SSA phases, following VSX swap removal. A pass of dead code
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// elimination follows this one for quick clean-up of any dead
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// instructions introduced here. Although we could do this as callbacks
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// from the generic peephole pass, this would have a couple of bad
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// effects: it might remove optimization opportunities for VSX swap
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// removal, and it would miss cleanups made possible following VSX
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// swap removal.
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//
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//===---------------------------------------------------------------------===//
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#include "PPCInstrInfo.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-mi-peepholes"
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namespace llvm {
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void initializePPCMIPeepholePass(PassRegistry&);
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}
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namespace {
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struct PPCMIPeephole : public MachineFunctionPass {
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static char ID;
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const PPCInstrInfo *TII;
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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PPCMIPeephole() : MachineFunctionPass(ID) {
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initializePPCMIPeepholePass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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// Perform peepholes.
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bool simplifyCode(void);
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// Find the "true" register represented by SrcReg (following chains
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// of copies and subreg_to_reg operations).
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unsigned lookThruCopyLike(unsigned SrcReg);
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(*MF.getFunction()))
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return false;
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initialize(MF);
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return simplifyCode();
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}
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};
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// Initialize class variables.
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void PPCMIPeephole::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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MRI = &MF->getRegInfo();
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TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
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DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
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DEBUG(MF->dump());
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}
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// Perform peephole optimizations.
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bool PPCMIPeephole::simplifyCode(void) {
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bool Simplified = false;
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MachineInstr* ToErase = nullptr;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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// If the previous instruction was marked for elimination,
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// remove it now.
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// Ignore debug instructions.
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if (MI.isDebugValue())
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continue;
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// Per-opcode peepholes.
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switch (MI.getOpcode()) {
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default:
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break;
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case PPC::XXPERMDI: {
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// Perform simplifications of 2x64 vector swaps and splats.
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// A swap is identified by an immediate value of 2, and a splat
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// is identified by an immediate value of 0 or 3.
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int Immed = MI.getOperand(3).getImm();
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if (Immed != 1) {
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// For each of these simplifications, we need the two source
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// regs to match. Unfortunately, MachineCSE ignores COPY and
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// SUBREG_TO_REG, so for example we can see
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// XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
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// We have to look through chains of COPY and SUBREG_TO_REG
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// to find the real source values for comparison.
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unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg());
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unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg());
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if (TrueReg1 == TrueReg2
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&& TargetRegisterInfo::isVirtualRegister(TrueReg1)) {
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MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
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unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0;
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// If this is a splat fed by a splatting load, the splat is
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// redundant. Replace with a copy. This doesn't happen directly due
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// to code in PPCDAGToDAGISel.cpp, but it can happen when converting
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// a load of a double to a vector of 64-bit integers.
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auto isConversionOfLoadAndSplat = [=]() -> bool {
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if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
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return false;
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unsigned DefReg = lookThruCopyLike(DefMI->getOperand(1).getReg());
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if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
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MachineInstr *LoadMI = MRI->getVRegDef(DefReg);
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if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
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return true;
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}
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return false;
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};
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if (DefMI && (Immed == 0 || Immed == 3)) {
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if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) {
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DEBUG(dbgs()
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<< "Optimizing load-and-splat/splat "
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"to load-and-splat/copy: ");
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DEBUG(MI.dump());
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
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MI.getOperand(0).getReg())
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.add(MI.getOperand(1));
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ToErase = &MI;
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Simplified = true;
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}
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}
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// If this is a splat or a swap fed by another splat, we
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// can replace it with a copy.
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if (DefOpc == PPC::XXPERMDI) {
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unsigned FeedImmed = DefMI->getOperand(3).getImm();
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unsigned FeedReg1
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= lookThruCopyLike(DefMI->getOperand(1).getReg());
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unsigned FeedReg2
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= lookThruCopyLike(DefMI->getOperand(2).getReg());
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if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) {
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DEBUG(dbgs()
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<< "Optimizing splat/swap or splat/splat "
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"to splat/copy: ");
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DEBUG(MI.dump());
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
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MI.getOperand(0).getReg())
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.add(MI.getOperand(1));
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ToErase = &MI;
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Simplified = true;
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}
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// If this is a splat fed by a swap, we can simplify modify
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// the splat to splat the other value from the swap's input
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// parameter.
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else if ((Immed == 0 || Immed == 3)
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&& FeedImmed == 2 && FeedReg1 == FeedReg2) {
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DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
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DEBUG(MI.dump());
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MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
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MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
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MI.getOperand(3).setImm(3 - Immed);
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Simplified = true;
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}
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// If this is a swap fed by a swap, we can replace it
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// with a copy from the first swap's input.
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else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) {
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DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
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DEBUG(MI.dump());
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
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MI.getOperand(0).getReg())
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.add(DefMI->getOperand(1));
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ToErase = &MI;
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Simplified = true;
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}
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} else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs &&
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(DefMI->getOperand(2).getImm() == 0 ||
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DefMI->getOperand(2).getImm() == 3)) {
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// Splat fed by another splat - switch the output of the first
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// and remove the second.
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DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
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ToErase = &MI;
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Simplified = true;
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DEBUG(dbgs() << "Removing redundant splat: ");
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DEBUG(MI.dump());
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}
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}
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}
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break;
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}
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case PPC::VSPLTB:
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case PPC::VSPLTH:
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case PPC::XXSPLTW: {
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unsigned MyOpcode = MI.getOpcode();
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unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
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unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg());
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if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
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break;
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MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
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if (!DefMI)
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break;
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unsigned DefOpcode = DefMI->getOpcode();
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auto isConvertOfSplat = [=]() -> bool {
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if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
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return false;
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unsigned ConvReg = DefMI->getOperand(1).getReg();
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if (!TargetRegisterInfo::isVirtualRegister(ConvReg))
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return false;
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MachineInstr *Splt = MRI->getVRegDef(ConvReg);
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return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
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Splt->getOpcode() == PPC::XXSPLTW);
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};
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bool AlreadySplat = (MyOpcode == DefOpcode) ||
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(MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
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(MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
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(MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
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// If the instruction[s] that feed this splat have already splat
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// the value, this splat is redundant.
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if (AlreadySplat) {
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DEBUG(dbgs() << "Changing redundant splat to a copy: ");
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DEBUG(MI.dump());
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
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MI.getOperand(0).getReg())
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.add(MI.getOperand(OpNo));
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ToErase = &MI;
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Simplified = true;
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}
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// Splat fed by a shift. Usually when we align value to splat into
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// vector element zero.
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if (DefOpcode == PPC::XXSLDWI) {
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unsigned ShiftRes = DefMI->getOperand(0).getReg();
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unsigned ShiftOp1 = DefMI->getOperand(1).getReg();
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unsigned ShiftOp2 = DefMI->getOperand(2).getReg();
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unsigned ShiftImm = DefMI->getOperand(3).getImm();
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unsigned SplatImm = MI.getOperand(2).getImm();
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if (ShiftOp1 == ShiftOp2) {
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unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
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if (MRI->hasOneNonDBGUse(ShiftRes)) {
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DEBUG(dbgs() << "Removing redundant shift: ");
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DEBUG(DefMI->dump());
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ToErase = DefMI;
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}
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Simplified = true;
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DEBUG(dbgs() << "Changing splat immediate from " << SplatImm <<
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" to " << NewElem << " in instruction: ");
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DEBUG(MI.dump());
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MI.getOperand(1).setReg(ShiftOp1);
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MI.getOperand(2).setImm(NewElem);
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}
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}
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break;
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}
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case PPC::XVCVDPSP: {
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// If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
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unsigned TrueReg = lookThruCopyLike(MI.getOperand(1).getReg());
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if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
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break;
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MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
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// This can occur when building a vector of single precision or integer
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// values.
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if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
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unsigned DefsReg1 = lookThruCopyLike(DefMI->getOperand(1).getReg());
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unsigned DefsReg2 = lookThruCopyLike(DefMI->getOperand(2).getReg());
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if (!TargetRegisterInfo::isVirtualRegister(DefsReg1) ||
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!TargetRegisterInfo::isVirtualRegister(DefsReg2))
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break;
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MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
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MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
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if (!P1 || !P2)
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break;
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// Remove the passed FRSP instruction if it only feeds this MI and
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// set any uses of that FRSP (in this MI) to the source of the FRSP.
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auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
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if (RoundInstr->getOpcode() == PPC::FRSP &&
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MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
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Simplified = true;
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unsigned ConvReg1 = RoundInstr->getOperand(1).getReg();
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unsigned FRSPDefines = RoundInstr->getOperand(0).getReg();
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MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
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for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
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if (Use.getOperand(i).isReg() &&
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Use.getOperand(i).getReg() == FRSPDefines)
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Use.getOperand(i).setReg(ConvReg1);
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DEBUG(dbgs() << "Removing redundant FRSP:\n");
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DEBUG(RoundInstr->dump());
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DEBUG(dbgs() << "As it feeds instruction:\n");
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DEBUG(MI.dump());
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DEBUG(dbgs() << "Through instruction:\n");
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DEBUG(DefMI->dump());
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RoundInstr->eraseFromParent();
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}
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};
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// If the input to XVCVDPSP is a vector that was built (even
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// partially) out of FRSP's, the FRSP(s) can safely be removed
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// since this instruction performs the same operation.
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if (P1 != P2) {
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removeFRSPIfPossible(P1);
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removeFRSPIfPossible(P2);
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break;
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}
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removeFRSPIfPossible(P1);
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}
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break;
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}
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}
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}
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// If the last instruction was marked for elimination,
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// remove it now.
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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}
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return Simplified;
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}
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// This is used to find the "true" source register for an
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// XXPERMDI instruction, since MachineCSE does not handle the
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// "copy-like" operations (Copy and SubregToReg). Returns
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// the original SrcReg unless it is the target of a copy-like
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// operation, in which case we chain backwards through all
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// such operations to the ultimate source register. If a
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// physical register is encountered, we stop the search.
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unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
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while (true) {
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MachineInstr *MI = MRI->getVRegDef(SrcReg);
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if (!MI->isCopyLike())
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return SrcReg;
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unsigned CopySrcReg;
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if (MI->isCopy())
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CopySrcReg = MI->getOperand(1).getReg();
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else {
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assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
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CopySrcReg = MI->getOperand(2).getReg();
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}
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if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg))
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return CopySrcReg;
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SrcReg = CopySrcReg;
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}
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}
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} // end default namespace
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INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
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"PowerPC MI Peephole Optimization", false, false)
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INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
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"PowerPC MI Peephole Optimization", false, false)
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char PPCMIPeephole::ID = 0;
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FunctionPass*
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llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
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