550 lines
20 KiB
C++
550 lines
20 KiB
C++
//===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZFrameLowering.h"
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#include "SystemZCallingConv.h"
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#include "SystemZInstrBuilder.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZRegisterInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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using namespace llvm;
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namespace {
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// The ABI-defined register save slots, relative to the incoming stack
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// pointer.
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static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
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{ SystemZ::R2D, 0x10 },
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{ SystemZ::R3D, 0x18 },
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{ SystemZ::R4D, 0x20 },
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{ SystemZ::R5D, 0x28 },
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{ SystemZ::R6D, 0x30 },
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{ SystemZ::R7D, 0x38 },
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{ SystemZ::R8D, 0x40 },
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{ SystemZ::R9D, 0x48 },
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{ SystemZ::R10D, 0x50 },
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{ SystemZ::R11D, 0x58 },
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{ SystemZ::R12D, 0x60 },
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{ SystemZ::R13D, 0x68 },
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{ SystemZ::R14D, 0x70 },
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{ SystemZ::R15D, 0x78 },
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{ SystemZ::F0D, 0x80 },
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{ SystemZ::F2D, 0x88 },
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{ SystemZ::F4D, 0x90 },
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{ SystemZ::F6D, 0x98 }
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};
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} // end anonymous namespace
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SystemZFrameLowering::SystemZFrameLowering()
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
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-SystemZMC::CallFrameSize, 8,
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false /* StackRealignable */) {
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// Create a mapping from register number to save slot offset.
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RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
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for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
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RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
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}
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const TargetFrameLowering::SpillSlot *
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SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
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NumEntries = array_lengthof(SpillOffsetTable);
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return SpillOffsetTable;
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}
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void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
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BitVector &SavedRegs,
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RegScavenger *RS) const {
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TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
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MachineFrameInfo &MFFrame = MF.getFrameInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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bool HasFP = hasFP(MF);
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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bool IsVarArg = MF.getFunction()->isVarArg();
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// va_start stores incoming FPR varargs in the normal way, but delegates
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// the saving of incoming GPR varargs to spillCalleeSavedRegisters().
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// Record these pending uses, which typically include the call-saved
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// argument register R6D.
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if (IsVarArg)
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for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
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SavedRegs.set(SystemZ::ArgGPRs[I]);
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// If there are any landing pads, entering them will modify r6/r7.
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if (!MF.getLandingPads().empty()) {
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SavedRegs.set(SystemZ::R6D);
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SavedRegs.set(SystemZ::R7D);
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}
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// If the function requires a frame pointer, record that the hard
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// frame pointer will be clobbered.
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if (HasFP)
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SavedRegs.set(SystemZ::R11D);
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// If the function calls other functions, record that the return
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// address register will be clobbered.
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if (MFFrame.hasCalls())
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SavedRegs.set(SystemZ::R14D);
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// If we are saving GPRs other than the stack pointer, we might as well
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// save and restore the stack pointer at the same time, via STMG and LMG.
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// This allows the deallocation to be done by the LMG, rather than needing
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// a separate %r15 addition.
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const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
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for (unsigned I = 0; CSRegs[I]; ++I) {
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unsigned Reg = CSRegs[I];
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if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
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SavedRegs.set(SystemZ::R15D);
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break;
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}
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}
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}
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// Add GPR64 to the save instruction being built by MIB, which is in basic
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// block MBB. IsImplicit says whether this is an explicit operand to the
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// instruction, or an implicit one that comes between the explicit start
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// and end registers.
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static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
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unsigned GPR64, bool IsImplicit) {
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const TargetRegisterInfo *RI =
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MBB.getParent()->getSubtarget().getRegisterInfo();
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unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
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bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
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if (!IsLive || !IsImplicit) {
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MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
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if (!IsLive)
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MBB.addLiveIn(GPR64);
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}
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}
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bool SystemZFrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
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bool IsVarArg = MF.getFunction()->isVarArg();
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DebugLoc DL;
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// Scan the call-saved GPRs and find the bounds of the register spill area.
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unsigned LowGPR = 0;
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unsigned HighGPR = SystemZ::R15D;
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unsigned StartOffset = -1U;
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (SystemZ::GR64BitRegClass.contains(Reg)) {
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unsigned Offset = RegSpillOffsets[Reg];
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assert(Offset && "Unexpected GPR save");
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if (StartOffset > Offset) {
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LowGPR = Reg;
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StartOffset = Offset;
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}
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}
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}
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// Save the range of call-saved registers, for use by the epilogue inserter.
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ZFI->setLowSavedGPR(LowGPR);
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ZFI->setHighSavedGPR(HighGPR);
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// Include the GPR varargs, if any. R6D is call-saved, so would
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// be included by the loop above, but we also need to handle the
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// call-clobbered argument registers.
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if (IsVarArg) {
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unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
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if (FirstGPR < SystemZ::NumArgGPRs) {
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unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
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unsigned Offset = RegSpillOffsets[Reg];
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if (StartOffset > Offset) {
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LowGPR = Reg; StartOffset = Offset;
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}
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}
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}
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// Save GPRs
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if (LowGPR) {
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assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
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// Build an STMG instruction.
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
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// Add the explicit register operands.
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addSavedGPR(MBB, MIB, LowGPR, false);
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addSavedGPR(MBB, MIB, HighGPR, false);
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// Add the address.
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MIB.addReg(SystemZ::R15D).addImm(StartOffset);
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// Make sure all call-saved GPRs are included as operands and are
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// marked as live on entry.
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (SystemZ::GR64BitRegClass.contains(Reg))
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addSavedGPR(MBB, MIB, Reg, true);
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}
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// ...likewise GPR varargs.
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if (IsVarArg)
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for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
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addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
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}
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// Save FPRs in the normal TargetInstrInfo way.
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (SystemZ::FP64BitRegClass.contains(Reg)) {
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MBB.addLiveIn(Reg);
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TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
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&SystemZ::FP64BitRegClass, TRI);
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}
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}
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return true;
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}
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bool SystemZFrameLowering::
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
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bool HasFP = hasFP(MF);
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Restore FPRs in the normal TargetInstrInfo way.
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (SystemZ::FP64BitRegClass.contains(Reg))
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TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
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&SystemZ::FP64BitRegClass, TRI);
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}
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// Restore call-saved GPRs (but not call-clobbered varargs, which at
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// this point might hold return values).
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unsigned LowGPR = ZFI->getLowSavedGPR();
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unsigned HighGPR = ZFI->getHighSavedGPR();
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unsigned StartOffset = RegSpillOffsets[LowGPR];
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if (LowGPR) {
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// If we saved any of %r2-%r5 as varargs, we should also be saving
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// and restoring %r6. If we're saving %r6 or above, we should be
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// restoring it too.
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assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
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// Build an LMG instruction.
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
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// Add the explicit register operands.
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MIB.addReg(LowGPR, RegState::Define);
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MIB.addReg(HighGPR, RegState::Define);
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// Add the address.
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MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
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MIB.addImm(StartOffset);
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// Do a second scan adding regs as being defined by instruction
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (Reg != LowGPR && Reg != HighGPR &&
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SystemZ::GR64BitRegClass.contains(Reg))
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MIB.addReg(Reg, RegState::ImplicitDefine);
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}
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}
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return true;
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}
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void SystemZFrameLowering::
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processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS) const {
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MachineFrameInfo &MFFrame = MF.getFrameInfo();
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uint64_t MaxReach = (MFFrame.estimateStackSize(MF) +
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SystemZMC::CallFrameSize * 2);
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if (!isUInt<12>(MaxReach)) {
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// We may need register scavenging slots if some parts of the frame
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// are outside the reach of an unsigned 12-bit displacement.
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// Create 2 for the case where both addresses in an MVC are
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// out of range.
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RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
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RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
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}
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}
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// Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
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static void emitIncrement(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const DebugLoc &DL,
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unsigned Reg, int64_t NumBytes,
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const TargetInstrInfo *TII) {
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while (NumBytes) {
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unsigned Opcode;
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int64_t ThisVal = NumBytes;
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if (isInt<16>(NumBytes))
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Opcode = SystemZ::AGHI;
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else {
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Opcode = SystemZ::AGFI;
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// Make sure we maintain 8-byte stack alignment.
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int64_t MinVal = -uint64_t(1) << 31;
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int64_t MaxVal = (int64_t(1) << 31) - 8;
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if (ThisVal < MinVal)
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ThisVal = MinVal;
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else if (ThisVal > MaxVal)
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ThisVal = MaxVal;
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}
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MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
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.addReg(Reg).addImm(ThisVal);
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// The CC implicit def is dead.
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MI->getOperand(3).setIsDead();
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NumBytes -= ThisVal;
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}
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}
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void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineFrameInfo &MFFrame = MF.getFrameInfo();
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auto *ZII =
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static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
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SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
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bool HasFP = hasFP(MF);
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc DL;
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// The current offset of the stack pointer from the CFA.
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int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
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if (ZFI->getLowSavedGPR()) {
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// Skip over the GPR saves.
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if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
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++MBBI;
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else
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llvm_unreachable("Couldn't skip over GPR saves");
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// Add CFI for the GPR saves.
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for (auto &Save : CSI) {
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unsigned Reg = Save.getReg();
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if (SystemZ::GR64BitRegClass.contains(Reg)) {
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int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
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BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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}
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uint64_t StackSize = getAllocatedStackSize(MF);
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if (StackSize) {
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// Determine if we want to store a backchain.
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bool StoreBackchain = MF.getFunction()->hasFnAttribute("backchain");
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// If we need backchain, save current stack pointer. R1 is free at this
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// point.
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if (StoreBackchain)
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BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
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.addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
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// Allocate StackSize bytes.
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int64_t Delta = -int64_t(StackSize);
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emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
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// Add CFI for the allocation.
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
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BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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SPOffsetFromCFA += Delta;
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if (StoreBackchain)
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BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
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.addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
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}
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if (HasFP) {
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// Copy the base of the frame to R11.
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BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
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.addReg(SystemZ::R15D);
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// Add CFI for the new frame location.
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unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
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BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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// Mark the FramePtr as live at the beginning of every block except
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// the entry block. (We'll have marked R11 as live on entry when
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// saving the GPRs.)
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for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
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I->addLiveIn(SystemZ::R11D);
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}
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// Skip over the FPR saves.
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SmallVector<unsigned, 8> CFIIndexes;
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for (auto &Save : CSI) {
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unsigned Reg = Save.getReg();
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if (SystemZ::FP64BitRegClass.contains(Reg)) {
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if (MBBI != MBB.end() &&
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(MBBI->getOpcode() == SystemZ::STD ||
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MBBI->getOpcode() == SystemZ::STDY))
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++MBBI;
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else
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llvm_unreachable("Couldn't skip over FPR save");
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// Add CFI for the this save.
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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unsigned IgnoredFrameReg;
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int64_t Offset =
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getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, DwarfReg, SPOffsetFromCFA + Offset));
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CFIIndexes.push_back(CFIIndex);
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}
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}
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// Complete the CFI for the FPR saves, modelling them as taking effect
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// after the last save.
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for (auto CFIIndex : CFIIndexes) {
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BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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auto *ZII =
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static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
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SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
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// Skip the return instruction.
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assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
|
|
|
|
uint64_t StackSize = getAllocatedStackSize(MF);
|
|
if (ZFI->getLowSavedGPR()) {
|
|
--MBBI;
|
|
unsigned Opcode = MBBI->getOpcode();
|
|
if (Opcode != SystemZ::LMG)
|
|
llvm_unreachable("Expected to see callee-save register restore code");
|
|
|
|
unsigned AddrOpNo = 2;
|
|
DebugLoc DL = MBBI->getDebugLoc();
|
|
uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
|
|
unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
|
|
|
|
// If the offset is too large, use the largest stack-aligned offset
|
|
// and add the rest to the base register (the stack or frame pointer).
|
|
if (!NewOpcode) {
|
|
uint64_t NumBytes = Offset - 0x7fff8;
|
|
emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
|
|
NumBytes, ZII);
|
|
Offset -= NumBytes;
|
|
NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
|
|
assert(NewOpcode && "No restore instruction available");
|
|
}
|
|
|
|
MBBI->setDesc(ZII->get(NewOpcode));
|
|
MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
|
|
} else if (StackSize) {
|
|
DebugLoc DL = MBBI->getDebugLoc();
|
|
emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
|
|
}
|
|
}
|
|
|
|
bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
|
|
return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
|
|
MF.getFrameInfo().hasVarSizedObjects() ||
|
|
MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
|
|
}
|
|
|
|
int SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF,
|
|
int FI,
|
|
unsigned &FrameReg) const {
|
|
const MachineFrameInfo &MFFrame = MF.getFrameInfo();
|
|
const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
|
|
|
|
// Fill in FrameReg output argument.
|
|
FrameReg = RI->getFrameRegister(MF);
|
|
|
|
// Start with the offset of FI from the top of the caller-allocated frame
|
|
// (i.e. the top of the 160 bytes allocated by the caller). This initial
|
|
// offset is therefore negative.
|
|
int64_t Offset = (MFFrame.getObjectOffset(FI) +
|
|
MFFrame.getOffsetAdjustment());
|
|
|
|
// Make the offset relative to the incoming stack pointer.
|
|
Offset -= getOffsetOfLocalArea();
|
|
|
|
// Make the offset relative to the bottom of the frame.
|
|
Offset += getAllocatedStackSize(MF);
|
|
|
|
return Offset;
|
|
}
|
|
|
|
uint64_t SystemZFrameLowering::
|
|
getAllocatedStackSize(const MachineFunction &MF) const {
|
|
const MachineFrameInfo &MFFrame = MF.getFrameInfo();
|
|
|
|
// Start with the size of the local variables and spill slots.
|
|
uint64_t StackSize = MFFrame.getStackSize();
|
|
|
|
// We need to allocate the ABI-defined 160-byte base area whenever
|
|
// we allocate stack space for our own use and whenever we call another
|
|
// function.
|
|
if (StackSize || MFFrame.hasVarSizedObjects() || MFFrame.hasCalls())
|
|
StackSize += SystemZMC::CallFrameSize;
|
|
|
|
return StackSize;
|
|
}
|
|
|
|
bool
|
|
SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
|
// The ABI requires us to allocate 160 bytes of stack space for the callee,
|
|
// with any outgoing stack arguments being placed above that. It seems
|
|
// better to make that area a permanent feature of the frame even if
|
|
// we're using a frame pointer.
|
|
return true;
|
|
}
|
|
|
|
MachineBasicBlock::iterator SystemZFrameLowering::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const {
|
|
switch (MI->getOpcode()) {
|
|
case SystemZ::ADJCALLSTACKDOWN:
|
|
case SystemZ::ADJCALLSTACKUP:
|
|
assert(hasReservedCallFrame(MF) &&
|
|
"ADJSTACKDOWN and ADJSTACKUP should be no-ops");
|
|
return MBB.erase(MI);
|
|
break;
|
|
|
|
default:
|
|
llvm_unreachable("Unexpected call frame instruction");
|
|
}
|
|
}
|