359 lines
17 KiB
TableGen
359 lines
17 KiB
TableGen
//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 jump, return, call, and related instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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// Return instructions.
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//
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// The X86retflag return instructions are variadic because we may add ST0 and
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// ST1 arguments when returning values on the x87 stack.
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
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def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{l}", [], IIC_RET>, OpSize32,
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Requires<[Not64BitMode]>;
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def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{q}", [], IIC_RET>, OpSize32,
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Requires<[In64BitMode]>;
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def RETW : I <0xC3, RawFrm, (outs), (ins),
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"ret{w}",
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[], IIC_RET>, OpSize16;
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def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret{l}\t$amt",
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[], IIC_RET_IMM>, OpSize32,
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Requires<[Not64BitMode]>;
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def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret{q}\t$amt",
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[], IIC_RET_IMM>, OpSize32,
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Requires<[In64BitMode]>;
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def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
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"ret{w}\t$amt",
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[], IIC_RET_IMM>, OpSize16;
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def LRETL : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{l|f}", [], IIC_RET>, OpSize32;
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def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
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"{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
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def LRETW : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{w|f}", [], IIC_RET>, OpSize16;
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def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
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def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
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def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
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// The machine return from interrupt instruction, but sometimes we need to
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// perform a post-epilogue stack adjustment. Codegen emits the pseudo form
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// which expands to include an SP adjustment if necessary.
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def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>,
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OpSize16;
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def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", [],
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IIC_IRET>, OpSize32;
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def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", [],
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IIC_IRET>, Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>;
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def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>;
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}
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// Unconditional branches.
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let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
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let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
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}
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
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multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
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def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
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[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>;
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let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm,
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[], IIC_Jcc>, OpSize16, TB;
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def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm,
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[], IIC_Jcc>, TB, OpSize32;
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}
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}
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}
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defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
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defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
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defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
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defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
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defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
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defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
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defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
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defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
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defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
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defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
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defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
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defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
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defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
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defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
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defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
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defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
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// jcx/jecx/jrcx instructions.
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let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
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// These are the 32-bit versions of this instruction for the asmparser. In
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// 32-bit mode, the address size prefix is jcxz and the unprefixed version is
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// jecxz.
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let Uses = [CX] in
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def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jcxz\t$dst", [], IIC_JCXZ>, AdSize16,
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Requires<[Not64BitMode]>;
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let Uses = [ECX] in
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def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jecxz\t$dst", [], IIC_JCXZ>, AdSize32;
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let Uses = [RCX] in
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def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jrcxz\t$dst", [], IIC_JCXZ>, AdSize64,
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Requires<[In64BitMode]>;
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}
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
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[(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJump]>;
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def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
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[(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
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Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
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def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
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[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJump]>;
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def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
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[(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
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Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
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Sched<[WriteJump]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
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Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
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let Predicates = [Not64BitMode] in {
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def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"ljmp{w}\t$seg, $off", [],
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IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
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def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"ljmp{l}\t$seg, $off", [],
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IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
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}
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def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
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"ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
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Sched<[WriteJump]>;
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def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
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"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
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Sched<[WriteJumpLd]>;
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def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
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"ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
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Sched<[WriteJumpLd]>;
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}
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// Loop instructions
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let SchedRW = [WriteJump] in {
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def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
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def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
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def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Uses = [ESP] in {
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def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i32imm_pcrel:$dst),
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"call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
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Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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let hasSideEffects = 0 in
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def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
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(outs), (ins i16imm_pcrel:$dst),
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"call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
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Sched<[WriteJump]>;
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def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
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"call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
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OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
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"call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
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IIC_CALL_MEM>, OpSize16,
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Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>;
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def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
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"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
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OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
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"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
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IIC_CALL_MEM>, OpSize32,
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Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>;
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let Predicates = [Not64BitMode] in {
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def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"lcall{w}\t$seg, $off", [],
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IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
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def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"lcall{l}\t$seg, $off", [],
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IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
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}
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def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
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"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
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Sched<[WriteJumpLd]>;
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def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
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"lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
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Sched<[WriteJumpLd]>;
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}
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
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let Uses = [ESP] in {
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def TCRETURNdi : PseudoI<(outs),
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(ins i32imm_pcrel:$dst, i32imm:$offset), []>;
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def TCRETURNri : PseudoI<(outs),
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(ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
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let mayLoad = 1 in
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def TCRETURNmi : PseudoI<(outs),
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(ins i32mem_TC:$dst, i32imm:$offset), []>;
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// FIXME: The should be pseudo instructions that are lowered when going to
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// mcinst.
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def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
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(ins i32imm_pcrel:$dst),
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"jmp\t$dst",
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[], IIC_JMP_REL>;
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def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
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"", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
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let mayLoad = 1 in
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def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
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"jmp{l}\t{*}$dst", [], IIC_JMP_MEM>;
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}
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// Conditional tail calls are similar to the above, but they are branches
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// rather than barriers, and they use EFLAGS.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
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isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
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let Uses = [ESP, EFLAGS] in {
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def TCRETURNdicc : PseudoI<(outs),
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(ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>;
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// This gets substituted to a conditional jump instruction in MC lowering.
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def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs),
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(ins i32imm_pcrel:$dst, i32imm:$cond),
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"",
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[], IIC_JMP_REL>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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// RSP is marked as a use to prevent stack-pointer assignments that appear
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// immediately before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst),
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"call{q}\t$dst", [], IIC_CALL_RI>, OpSize32,
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Requires<[In64BitMode]>;
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def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
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"call{q}\t{*}$dst", [(X86call GR64:$dst)],
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IIC_CALL_RI>,
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Requires<[In64BitMode]>;
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def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
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"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
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IIC_CALL_MEM>,
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Requires<[In64BitMode,FavorMemIndirectCall]>;
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def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
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"lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
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}
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
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SchedRW = [WriteJump] in {
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def TCRETURNdi64 : PseudoI<(outs),
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(ins i64i32imm_pcrel:$dst, i32imm:$offset),
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[]>;
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def TCRETURNri64 : PseudoI<(outs),
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(ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
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let mayLoad = 1 in
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def TCRETURNmi64 : PseudoI<(outs),
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(ins i64mem_TC:$dst, i32imm:$offset), []>;
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def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>;
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def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
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"jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
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let mayLoad = 1 in
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def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
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"jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
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// Win64 wants indirect jumps leaving the function to have a REX_W prefix.
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let hasREX_WPrefix = 1 in {
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def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
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"rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
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let mayLoad = 1 in
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def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
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"rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
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}
|
|
}
|
|
|
|
// Conditional tail calls are similar to the above, but they are branches
|
|
// rather than barriers, and they use EFLAGS.
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
|
|
isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
|
|
let Uses = [RSP, EFLAGS] in {
|
|
def TCRETURNdi64cc : PseudoI<(outs),
|
|
(ins i64i32imm_pcrel:$dst, i32imm:$offset,
|
|
i32imm:$cond), []>;
|
|
|
|
// This gets substituted to a conditional jump instruction in MC lowering.
|
|
def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs),
|
|
(ins i64i32imm_pcrel:$dst, i32imm:$cond),
|
|
"",
|
|
[], IIC_JMP_REL>;
|
|
}
|