175 lines
5.1 KiB
LLVM
175 lines
5.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test_smul24_i32:
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; GCN-NOT: bfe
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; GCN: v_mul_i32_i24
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; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
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; EG: MULLO_INT
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; Make sure we are not masking the inputs
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; CM-NOT: AND
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; CM: MUL_INT24
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define void @test_smul24_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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entry:
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%a.shl = shl i32 %a, 8
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%a.24 = ashr i32 %a.shl, 8
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%b.shl = shl i32 %b, 8
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%b.24 = ashr i32 %b.shl, 8
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%mul24 = mul i32 %a.24, %b.24
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store i32 %mul24, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_smulhi24_i64:
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; GCN-NOT: bfe
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; GCN-NOT: ashr
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; GCN: v_mul_hi_i32_i24_e32 [[RESULT:v[0-9]+]],
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; GCN-NEXT: buffer_store_dword [[RESULT]]
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; EG: ASHR
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; EG: ASHR
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; EG: MULHI_INT
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; CM-NOT: ASHR
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; CM: MULHI_INT24
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; CM: MULHI_INT24
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; CM: MULHI_INT24
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; CM: MULHI_INT24
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define void @test_smulhi24_i64(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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entry:
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%a.shl = shl i32 %a, 8
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%a.24 = ashr i32 %a.shl, 8
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%b.shl = shl i32 %b, 8
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%b.24 = ashr i32 %b.shl, 8
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%a.24.i64 = sext i32 %a.24 to i64
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%b.24.i64 = sext i32 %b.24 to i64
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%mul48 = mul i64 %a.24.i64, %b.24.i64
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%mul48.hi = lshr i64 %mul48, 32
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%mul24hi = trunc i64 %mul48.hi to i32
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store i32 %mul24hi, i32 addrspace(1)* %out
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ret void
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}
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; This requires handling of the original 64-bit mul node to eliminate
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; unnecessary extension instructions because after legalization they
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; will not be removed by SimplifyDemandedBits because there are
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; multiple uses by the separate mul and mulhi.
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; FUNC-LABEL: {{^}}test_smul24_i64:
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; GCN: s_load_dword s
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; GCN: s_load_dword s
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; GCN-NOT: bfe
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; GCN-NOT: ashr
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; GCN-DAG: v_mul_hi_i32_i24_e32
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; GCN-DAG: v_mul_i32_i24_e32
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; GCN: buffer_store_dwordx2
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define void @test_smul24_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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%shl.i = shl i32 %a, 8
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%shr.i = ashr i32 %shl.i, 8
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%conv.i = sext i32 %shr.i to i64
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%shl1.i = shl i32 %b, 8
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%shr2.i = ashr i32 %shl1.i, 8
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%conv3.i = sext i32 %shr2.i to i64
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%mul.i = mul i64 %conv3.i, %conv.i
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store i64 %mul.i, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_smul24_i64_square:
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; GCN: s_load_dword [[A:s[0-9]+]]
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; GCN-DAG: v_mul_hi_i32_i24_e64 v{{[0-9]+}}, [[A]], [[A]]
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; GCN-DAG: v_mul_i32_i24_e64 v{{[0-9]+}}, [[A]], [[A]]
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; GCN: buffer_store_dwordx2
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define void @test_smul24_i64_square(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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%shl.i = shl i32 %a, 8
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%shr.i = ashr i32 %shl.i, 8
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%conv.i = sext i32 %shr.i to i64
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%mul.i = mul i64 %conv.i, %conv.i
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store i64 %mul.i, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_smul24_i33:
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; GCN: s_load_dword s
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; GCN: s_load_dword s
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; GCN-NOT: and
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; GCN-NOT: lshr
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; GCN-DAG: v_mul_i32_i24_e32
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; GCN-DAG: v_mul_hi_i32_i24_e32
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; SI: v_lshl_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 31
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; SI: v_ashr_i64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 31
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; VI: v_lshlrev_b64 v{{\[[0-9]+:[0-9]+\]}}, 31, v{{\[[0-9]+:[0-9]+\]}}
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; VI: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 31, v{{\[[0-9]+:[0-9]+\]}}
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; GCN: buffer_store_dwordx2
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define void @test_smul24_i33(i64 addrspace(1)* %out, i33 %a, i33 %b) #0 {
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entry:
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%a.shl = shl i33 %a, 9
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%a.24 = ashr i33 %a.shl, 9
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%b.shl = shl i33 %b, 9
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%b.24 = ashr i33 %b.shl, 9
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%mul24 = mul i33 %a.24, %b.24
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%ext = sext i33 %mul24 to i64
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store i64 %ext, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_smulhi24_i33:
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; SI: s_load_dword s
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; SI: s_load_dword s
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; SI-NOT: bfe
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; SI: v_mul_hi_i32_i24_e32 v[[MUL_HI:[0-9]+]],
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; SI-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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; SI-NEXT: buffer_store_dword v[[HI]]
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define void @test_smulhi24_i33(i32 addrspace(1)* %out, i33 %a, i33 %b) {
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entry:
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%tmp0 = shl i33 %a, 9
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%a_24 = ashr i33 %tmp0, 9
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%tmp1 = shl i33 %b, 9
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%b_24 = ashr i33 %tmp1, 9
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%tmp2 = mul i33 %a_24, %b_24
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%hi = lshr i33 %tmp2, 32
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%trunc = trunc i33 %hi to i32
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store i32 %trunc, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}simplify_i24_crash:
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; GCN: v_mul_i32_i24_e32 v[[VAL_LO:[0-9]+]]
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; GCN: v_mov_b32_e32 v[[VAL_HI:[0-9]+]], v[[VAL_LO]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
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define void @simplify_i24_crash(<2 x i32> addrspace(1)* %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) {
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bb:
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%cmp = icmp eq i32 %arg0, 0
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br i1 %cmp, label %bb11, label %bb7
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bb11:
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%tmp14 = shufflevector <2 x i32> %arg1, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp16 = shufflevector <2 x i32> %arg2, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp17 = shl <2 x i32> %tmp14, <i32 8, i32 8>
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%tmp18 = ashr <2 x i32> %tmp17, <i32 8, i32 8>
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%tmp19 = shl <2 x i32> %tmp16, <i32 8, i32 8>
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%tmp20 = ashr <2 x i32> %tmp19, <i32 8, i32 8>
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%tmp21 = mul <2 x i32> %tmp18, %tmp20
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store <2 x i32> %tmp21, <2 x i32> addrspace(1)* %out
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br label %bb7
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bb7:
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ret void
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}
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attributes #0 = { nounwind }
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