39 lines
1.5 KiB
ArmAsm
39 lines
1.5 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -instruction-tables < %s | FileCheck %s
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prefetch (%rax)
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prefetchw (%rax)
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
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# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - BWDivider
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# CHECK-NEXT: [1] - BWFPDivider
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# CHECK-NEXT: [2] - BWPort0
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# CHECK-NEXT: [3] - BWPort1
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# CHECK-NEXT: [4] - BWPort2
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# CHECK-NEXT: [5] - BWPort3
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# CHECK-NEXT: [6] - BWPort4
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# CHECK-NEXT: [7] - BWPort5
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# CHECK-NEXT: [8] - BWPort6
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# CHECK-NEXT: [9] - BWPort7
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
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# CHECK-NEXT: - - - - 1.00 1.00 - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetch (%rax)
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# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetchw (%rax)
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