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AsmParser
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[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
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2021-11-04 10:08:01 -07:00 |
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Disassembler
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Move TargetRegistry.(h|cpp) from Support to MC
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2021-10-08 14:51:48 -07:00 |
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MCTargetDesc
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[RISCV] Decode vtype with reserved fields to raw immediate
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2021-11-30 08:31:20 +00:00 |
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TargetInfo
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Fix shlib builds for all lib/Target/*/TargetInfo libs
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2021-10-08 15:21:13 -07:00 |
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CMakeLists.txt
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[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
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2021-09-20 09:39:44 -07:00 |
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RISCV.h
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[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
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2021-09-20 09:39:44 -07:00 |
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RISCV.td
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[RISCV] Support Zfhmin extension
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2021-11-06 01:41:02 +08:00 |
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RISCVAsmPrinter.cpp
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Move TargetRegistry.(h|cpp) from Support to MC
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2021-10-08 14:51:48 -07:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
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2021-10-02 10:44:11 -07:00 |
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RISCVFrameLowering.cpp
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[RISCV] Fix a bug in RISCVFrameLowering.
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2021-11-30 10:39:35 +08:00 |
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RISCVFrameLowering.h
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[RISCV] Enable shrink wrap by default
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2021-09-02 09:47:58 -05:00 |
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RISCVGatherScatterLowering.cpp
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[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
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2021-10-27 19:33:48 -07:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
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2021-11-04 10:08:01 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
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2021-09-24 17:09:50 +08:00 |
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RISCVISelLowering.cpp
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[RISCV][VP] Add RVV codegen for vp.select
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2021-12-03 11:02:20 +00:00 |
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RISCVISelLowering.h
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[DAG] Create fptosi.sat from clamped fptosi
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2021-11-30 15:29:14 +00:00 |
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RISCVInsertVSETVLI.cpp
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[RISCV] Teach needVSETVLIPHI to handle mask register instructions.
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2021-11-15 09:57:28 -08:00 |
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RISCVInstrFormats.td
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[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
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2021-10-28 11:39:04 +08:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
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[CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress
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2021-11-17 10:16:47 +00:00 |
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RISCVInstrInfo.h
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[CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress
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2021-11-17 10:16:47 +00:00 |
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RISCVInstrInfo.td
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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RISCVInstrInfoA.td
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[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
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2021-04-09 09:37:04 +08:00 |
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RISCVInstrInfoC.td
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[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
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2021-11-18 11:14:27 +08:00 |
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RISCVInstrInfoD.td
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[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
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2021-08-07 16:06:00 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
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2021-08-07 16:06:00 -07:00 |
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RISCVInstrInfoM.td
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[RISCV] Improve codegen for i32 udiv/urem by constant on RV64.
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2021-11-12 14:49:10 -08:00 |
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RISCVInstrInfoV.td
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[RISCV] Refactor some rvv instructions' definition with foreach.
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2021-11-16 15:20:45 +08:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
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2021-11-04 10:08:01 -07:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
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2021-11-04 10:08:01 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
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2021-11-04 10:08:01 -07:00 |
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RISCVInstrInfoZb.td
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[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.
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2021-10-14 09:25:03 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Support Zfhmin extension
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2021-11-06 01:41:02 +08:00 |
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RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
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2021-06-01 13:23:48 -07:00 |
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
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2021-08-04 10:39:50 -07:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Don't emit save-restore call if function is a interrupt handler
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2021-04-16 12:54:47 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Remove unused member variable. NFC
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2021-10-14 12:56:47 -07:00 |
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Emit DWARF location expression for RVV stack objects.
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2021-11-27 15:13:10 +08:00 |
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RISCVRegisterInfo.h
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[RISCV] Emit DWARF location expression for RVV stack objects.
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2021-11-27 15:13:10 +08:00 |
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RISCVRegisterInfo.td
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[RISCV] Emit DWARF location expression for RVV stack objects.
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2021-11-27 15:13:10 +08:00 |
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RISCVSchedRocket.td
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[RISCV] Add scheduling resources for V
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2021-08-03 15:47:51 -05:00 |
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RISCVSchedSiFive7.td
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[RISCV] Fix typo in RISCVSchedSiFive7.td
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2021-09-01 16:39:48 -05:00 |
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RISCVSchedule.td
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[RISCV] Add scheduling resources for V
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2021-08-03 15:47:51 -05:00 |
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RISCVScheduleB.td
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[RISCV] Move scheduling resources for B into a separate file (NFC)
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2021-03-29 20:37:22 -05:00 |
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RISCVScheduleV.td
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[RISCV] Add scheduling resources for V
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2021-08-03 15:47:51 -05:00 |
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RISCVSubtarget.cpp
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[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
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2021-10-27 19:33:48 -07:00 |
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RISCVSubtarget.h
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[RISCV] Support Zfhmin extension
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2021-11-06 01:41:02 +08:00 |
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RISCVSystemOperands.td
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[RISCV] Emit DWARF location expression for RVV stack objects.
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2021-11-27 15:13:10 +08:00 |
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RISCVTargetMachine.cpp
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Move TargetRegistry.(h|cpp) from Support to MC
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2021-10-08 14:51:48 -07:00 |
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RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
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2021-10-27 19:33:48 -07:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
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2021-10-27 19:33:48 -07:00 |
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