Sam Elliott f596f45070 [RISCV] Add Custom Parser for Atomic Memory Operands ... Summary: GCC Accepts both (reg) and 0(reg) for atomic instruction memory operands. These instructions do not allow for an offset in their encoding, so in the latter case, the 0 is silently dropped. Due to how we have structured the RISCVAsmParser, the easiest way to add support for parsing this offset is to add a custom AsmOperand and parser. This parser drops all the parens, and just keeps the register. This commit also adds a custom printer for these operands, which matches the GCC canonical printer, printing both `(a0)` and `0(a0)` as `(a0)`. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: s.egerton, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65205 llvm-svn: 367553		2019-08-01 12:42:31 +00:00
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CMakeLists.txt	[RISCV] Move InstPrinter files to MCTargetDesc. NFC	2019-05-11 02:43:58 +00:00
LLVMBuild.txt	[RISCV] Move InstPrinter files to MCTargetDesc. NFC	2019-05-11 02:43:58 +00:00
RISCVAsmBackend.cpp	[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.	2019-07-19 02:03:34 +00:00
RISCVAsmBackend.h	[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers	2019-04-23 14:46:13 +00:00
RISCVELFObjectWriter.cpp	[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.	2019-07-19 02:03:34 +00:00
RISCVELFStreamer.cpp	[RISCV] Support -target-abi at the MC layer and for codegen	2019-03-09 09:28:06 +00:00
RISCVELFStreamer.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVFixupKinds.h	[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers	2019-04-23 14:46:13 +00:00
RISCVInstPrinter.cpp	[RISCV] Add Custom Parser for Atomic Memory Operands	2019-08-01 12:42:31 +00:00
RISCVInstPrinter.h	[RISCV] Add Custom Parser for Atomic Memory Operands	2019-08-01 12:42:31 +00:00
RISCVMCAsmInfo.cpp	[RISCV] Add CFI directives for RISCV prologue/epilog.	2019-06-12 03:04:22 +00:00
RISCVMCAsmInfo.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVMCCodeEmitter.cpp	[RISCV] Add pseudo instruction for calls with explicit register	2019-06-26 10:35:58 +00:00
RISCVMCExpr.cpp	[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers	2019-04-23 14:46:13 +00:00
RISCVMCExpr.h	[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers	2019-04-23 14:46:13 +00:00
RISCVMCTargetDesc.cpp	[RISCV] Add CFI directives for RISCV prologue/epilog.	2019-06-12 03:04:22 +00:00
RISCVMCTargetDesc.h	[RISCV] Create a TargetInfo header. NFC	2019-05-15 00:24:15 +00:00
RISCVTargetStreamer.cpp	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVTargetStreamer.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00