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AsmParser
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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Disassembler
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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GISel
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[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
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2022-11-15 14:24:50 -08:00 |
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MCTargetDesc
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[WORKAROUND] Do not use ABI register name yet
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2022-12-21 17:40:19 +08:00 |
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TargetInfo
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[RISCV] Re-enable JIT support
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2022-08-11 11:41:02 +02:00 |
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CMakeLists.txt
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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RISCV.h
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Add OpenCL addressing space mapping to RISCVAS.
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2022-12-20 17:08:08 +08:00 |
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RISCV.td
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
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RISCVAsmPrinter.cpp
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Restore code which enables MC emitter
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2022-12-21 17:40:19 +08:00 |
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RISCVCallingConv.td
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…
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RISCVCodeGenPrepare.cpp
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[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
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2022-08-12 22:21:05 -07:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
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2022-08-17 13:49:15 +01:00 |
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RISCVExpandPseudoInsts.cpp
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In the middle of removing RVV code.
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2022-12-16 18:04:43 +08:00 |
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RISCVFrameLowering.cpp
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Initially add vector load/store instruction and related codegen
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2022-12-21 16:27:39 +08:00 |
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RISCVFrameLowering.h
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[RISCV] Inline RISCVFrameLowering::adjustReg out of existance [nfc]
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2022-11-30 11:07:45 -08:00 |
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RISCVISelDAGToDAG.cpp
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Add basic support to select vALU load/store instruction.
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2022-12-22 10:55:14 +08:00 |
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RISCVISelDAGToDAG.h
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Add basic support to select vALU load/store instruction.
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2022-12-22 10:55:14 +08:00 |
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RISCVISelLowering.cpp
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Add initial support to lower ISD::SELECT into branch instructions in divergent execution path.
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2022-12-22 17:17:02 +08:00 |
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RISCVISelLowering.h
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[NFC] Refactor messy switch...case
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2022-12-22 14:50:13 +08:00 |
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RISCVInstrFormats.td
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Add vALU conditional branch instructions
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2022-12-19 13:09:00 +08:00 |
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RISCVInstrFormatsC.td
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…
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RISCVInstrFormatsV.td
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[RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC
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2022-11-30 20:58:40 -08:00 |
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RISCVInstrInfo.cpp
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Add initial support to lower ISD::SELECT into branch instructions in divergent execution path.
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2022-12-22 17:17:02 +08:00 |
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RISCVInstrInfo.h
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Add initial support to lower ISD::SELECT into branch instructions in divergent execution path.
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2022-12-22 17:17:02 +08:00 |
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RISCVInstrInfo.td
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[RISCV][NFC] Mark rs1 in most memory instructions as memory operand.
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2022-11-22 16:42:44 +03:00 |
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RISCVInstrInfoA.td
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[RISCV] Add target feature to force-enable atomics
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2022-08-09 16:04:46 +02:00 |
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RISCVInstrInfoC.td
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Add MC support of RISCV Zcd Extension
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2022-11-24 05:48:06 +08:00 |
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RISCVInstrInfoD.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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RISCVInstrInfoF.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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RISCVInstrInfoM.td
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[RISCV][Clang] Add support for Zmmul extension
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2022-07-18 20:26:08 -04:00 |
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RISCVInstrInfoV.td
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[RISCV][Codegen] Account for LMUL in Vector floating-point instructions
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2022-11-30 11:09:21 -08:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV][Codegen] Account for LMUL in Vector floating-point instructions
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2022-11-30 11:09:21 -08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber.
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2022-10-03 21:44:08 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[VP][RISCV] Add vp.nearbyint and RISC-V support.
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2022-11-16 14:05:35 +08:00 |
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RISCVInstrInfoXVentana.td
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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RISCVInstrInfoZb.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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RISCVInstrInfoZfh.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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RISCVInstrInfoZicbo.td
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[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
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2022-09-01 13:49:55 +01:00 |
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RISCVInstrInfoZk.td
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…
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RISCVMCInstLower.cpp
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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RISCVMachineFunctionInfo.cpp
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[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
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2022-10-04 15:39:10 -07:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
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2022-10-04 15:39:10 -07:00 |
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RISCVMacroFusion.cpp
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[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
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2022-08-21 10:58:15 -07:00 |
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RISCVMacroFusion.h
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[RISCV] Add macrofusion infrastructure and one example usage.
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2022-06-23 08:38:39 -07:00 |
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RISCVMakeCompressible.cpp
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[RISCV] Fix wrong register rename for store value during make-compressible optimization
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2022-07-08 18:07:17 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Use std::optional in RISCVMergeBaseOffset.cpp (NFC)
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2022-11-25 23:08:26 -08:00 |
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RISCVRedundantCopyElimination.cpp
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[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
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2022-08-29 09:05:53 -07:00 |
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RISCVRegisterInfo.cpp
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
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RISCVRegisterInfo.h
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
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RISCVRegisterInfo.td
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[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
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2022-08-24 14:16:20 +00:00 |
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RISCVSExtWRemoval.cpp
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[RISCV] Remove SExtWRemovalCands set from RISCVSExtWRemoval.
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2022-11-21 19:24:02 -08:00 |
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RISCVSchedRocket.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVSchedule.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVScheduleV.td
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[RISCV][Codegen] Account for LMUL in Vector floating-point instructions
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2022-11-30 11:09:21 -08:00 |
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RISCVScheduleZb.td
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[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
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2022-09-23 21:38:42 -07:00 |
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RISCVSearchableTables.td
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
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RISCVSubtarget.cpp
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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RISCVSubtarget.h
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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RISCVSystemOperands.td
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…
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RISCVTargetMachine.cpp
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Initially add vector load/store instruction and related codegen
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2022-12-21 16:27:39 +08:00 |
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RISCVTargetMachine.h
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Add OpenCL addressing space mapping to RISCVAS.
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2022-12-20 17:08:08 +08:00 |
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RISCVTargetObjectFile.cpp
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…
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RISCVTargetObjectFile.h
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…
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RISCVTargetTransformInfo.cpp
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
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RISCVTargetTransformInfo.h
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More clean up and fix build error.
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2022-12-19 10:10:28 +08:00 |
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VentusInstrFormatsV.td
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Add basic support to select vALU load/store instruction.
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2022-12-22 10:55:14 +08:00 |
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VentusInstrInfo.td
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Add initial support to lower ISD::SELECT into branch instructions in divergent execution path.
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2022-12-22 17:17:02 +08:00 |
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VentusInstrInfoA.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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VentusInstrInfoC.td
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Add initial support to lower ISD::SELECT into branch instructions in divergent execution path.
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2022-12-22 17:17:02 +08:00 |
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VentusInstrInfoM.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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VentusInstrInfoV.td
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Add initial support to lower ISD::SELECT into branch instructions in divergent execution path.
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2022-12-22 17:17:02 +08:00 |
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VentusInstrInfoVPseudos.td
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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VentusInstrInfoVSDPatterns.td
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Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td.
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2022-12-15 17:04:09 +08:00 |
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VentusInstrInfoVVLPatterns.td
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Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td.
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2022-12-15 17:04:09 +08:00 |
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VentusRegisterInfo.td
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
Aries
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