59 lines
2.2 KiB
C++
59 lines
2.2 KiB
C++
//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about RISCV target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
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}
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static std::string computeDataLayout(const Triple &TT) {
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if (TT.isArch64Bit()) {
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return "e-m:e-i64:64-n32:64-S128";
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} else {
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assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
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return "e-m:e-i64:64-n32-S128";
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}
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, RM), CM, OL),
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TLOF(make_unique<TargetLoweringObjectFileELF>()) {}
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TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(this, PM);
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}
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