Ulrich Weigand 33435c4c9c [SystemZ] Add support for IBM z14 processor (2/3) ... This adds support for the new 32-bit vector float instructions of z14. This includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions, including new LLVM intrinsics. - Scheduler description support for the instructions. - Update to the vector cost function calculations. In general, CodeGen support for the new v4f32 instructions closely matches support for the existing v2f64 instructions. llvm-svn: 308195		2017-07-17 17:42:48 +00:00
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AArch64	Revert r291254: [AArch64] Reduce vector insert/extract cost for Falkor	2017-05-24 16:48:39 +00:00
AMDGPU	AMDGPU: Make some packed shuffles free	2017-05-10 21:29:33 +00:00
ARM	[TTI/CostModel] Correct the way getGEPCost() calls isLegalAddressingMode()	2016-12-03 01:57:24 +00:00
PowerPC	[PPC] Give unaligned memory access lower cost on processor that supports it	2017-02-17 22:29:39 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (2/3)	2017-07-17 17:42:48 +00:00
X86	[X86][CM] update add\sub costs of vectors of 64 in X86\SLM arch	2017-07-02 12:16:15 +00:00
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