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llvm-project/llvm/lib/Target/RISCV/Disassembler
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Hsiangkai Wang 66da87dcba [RISCV] Assemble/Disassemble v-ext instructions. 
Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987
 		2020-06-28 00:54:07 +08:00
..
CMakeLists.txt [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries" 2019-11-21 10:48:08 -08:00
LLVMBuild.txt
…
RISCVDisassembler.cpp [RISCV] Assemble/Disassemble v-ext instructions. 2020-06-28 00:54:07 +08:00