Andrew Lenharth d4c0ed74e4 added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh ... llvm-svn: 23849		2005-10-20 19:39:24 +00:00
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Alpha	added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh	2005-10-20 19:39:24 +00:00
CBackend	fix CBackend/2005-09-27-VolatileFuncPtr.ll	2005-09-27 20:52:44 +00:00
IA64	Fix CodeGen/Generic/bool-to-double.ll	2005-10-07 04:50:48 +00:00
PowerPC	Add some more patterns for i64 on ppc	2005-10-20 07:51:08 +00:00
Skeleton	CR registers are not used by this "target"	2005-09-30 06:43:58 +00:00
SparcV8	silence some warnings	2005-10-05 17:15:09 +00:00
SparcV9	This fixes PR638:	2005-10-19 20:07:15 +00:00
X86	Remove some dead code now that the dag combiner exists.	2005-10-15 22:08:02 +00:00
MRegisterInfo.cpp	Rename MRegisterDesc -> TargetRegisterDesc for consistency	2005-09-30 17:49:27 +00:00
Makefile	Implement the --enable-targets= feature of the configure script. The make	2005-04-22 17:20:11 +00:00
SubtargetFeature.cpp	Print:	2005-09-07 05:44:14 +00:00
Target.td	Added InstrSchedClass to each of the PowerPC Instructions.	2005-10-19 19:51:16 +00:00
TargetData.cpp	Update to use the new MathExtras.h support for log2 computation.	2005-08-02 19:26:06 +00:00
TargetFrameInfo.cpp	Eliminate all remaining tabs and trailing spaces.	2005-07-27 06:12:32 +00:00
TargetInstrInfo.cpp	Convert tabs to spaces	2005-04-22 17:54:37 +00:00
TargetLowering.cpp	initialize new flag	2005-09-27 22:13:56 +00:00
TargetMachine.cpp	Remove the X86 and PowerPC Simple instruction selectors; their time has	2005-08-18 23:53:15 +00:00
TargetMachineRegistry.cpp	1. Use SubtargetFeatures in llc/lli.	2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp	Convert tabs to spaces	2005-04-22 17:54:37 +00:00
TargetSchedule.td	Push processor descriptions to the top of target and add command line info.	2005-10-19 13:34:52 +00:00
TargetSelectionDAG.td	add cttz and ctpop	2005-10-20 19:38:11 +00:00
TargetSubtarget.cpp	Eliminate all remaining tabs and trailing spaces.	2005-07-27 06:12:32 +00:00