llvm-project/llvm/lib/CodeGen/SelectionDAG
Dan Gohman 7867793aff Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.

Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.

llvm-svn: 37781
2007-06-28 23:29:44 +00:00
..
CallingConvLower.cpp add isVarArg to CCState 2007-06-19 00:11:09 +00:00
DAGCombiner.cpp Generalize MVT::ValueType and associated functions to be able to represent 2007-06-25 16:23:39 +00:00
LegalizeDAG.cpp Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT. 2007-06-27 16:08:04 +00:00
Makefile For PR780: 2006-07-26 16:18:00 +00:00
ScheduleDAG.cpp Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration 2007-06-19 14:13:56 +00:00
ScheduleDAGList.cpp switch the sched unit map over to use a DenseMap instead of std::map. This 2007-02-03 01:34:13 +00:00
ScheduleDAGRRList.cpp std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec. 2007-06-22 01:35:51 +00:00
ScheduleDAGSimple.cpp Removed tabs everywhere except autogenerated & external files. Add make 2007-04-16 18:10:23 +00:00
SelectionDAG.cpp Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT. 2007-06-27 16:08:04 +00:00
SelectionDAGISel.cpp Add new TargetLowering code to provide the final register type that an 2007-06-28 23:29:44 +00:00
SelectionDAGPrinter.cpp Make chain dependencies blue, in addition to being dashed. 2007-06-18 15:30:16 +00:00
TargetLowering.cpp Add new TargetLowering code to provide the final register type that an 2007-06-28 23:29:44 +00:00