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llvm-project/llvm/lib/Target/AMDGPU
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Tomas Matheson a9968c0a33 [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 
Currently needsStackRealignment returns false if canRealignStack returns false.
This means that the behavior of needsStackRealignment does not correspond to
it's name and description; a function might need stack realignment, but if it
is not possible then this function returns false. Furthermore,
needsStackRealignment is not virtual and therefore some backends have made use
of canRealignStack to indicate whether a function needs stack realignment.

This patch attempts to clarify the situation by separating them and introducing
new names:

 - shouldRealignStack - true if there is any reason the stack should be
   realigned

 - canRealignStack - true if we are still able to realign the stack (e.g. we
   can still reserve/have reserved a frame pointer)

 - hasStackRealignment = shouldRealignStack && canRealignStack (not target
   customisable)

Targets can now override shouldRealignStack to indicate that stack realignment
is required.

This change will make it easier in a future change to handle the case where we
need to realign the stack but can't do so (for example when the register
allocator creates an aligned spill after the frame pointer has been
eliminated).

Differential Revision: https://reviews.llvm.org/D98716

Change-Id: Ib9a4d21728bf9d08a545b4365418d3ffe1af4d87
 		2021-03-30 17:31:39 +01:00
..
AsmParser AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
Disassembler AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
MCTargetDesc AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
Utils AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPU.h [AMDGPU] Rename SIInsertSkips Pass 2021-03-20 11:48:04 +09:00
AMDGPU.td [AMDGPU] Split dot2-insts feature 2021-03-17 09:42:21 +00:00
AMDGPUAliasAnalysis.cpp [BasicAA] Always strip single-argument phi nodes 2021-02-18 23:07:50 +01:00
AMDGPUAliasAnalysis.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUAlwaysInlinePass.cpp [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
AMDGPUAnnotateKernelFeatures.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPUAnnotateUniformValues.cpp [AMDGPU] Simplify AMDGPUAnnotateUniformValues::visitBranchInst. NFC. 2021-03-23 16:54:43 +00:00
AMDGPUArgumentUsageInfo.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUArgumentUsageInfo.h [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
AMDGPUAsmPrinter.cpp AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPUAsmPrinter.h AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPUAtomicOptimizer.cpp [AMDGPU] Use reductions instead of scans in the atomic optimizer 2021-03-26 15:38:14 +00:00
AMDGPUCallLowering.cpp GlobalISel: Preserve source value information for outgoing byval args 2021-03-18 09:16:54 -04:00
AMDGPUCallLowering.h GlobalISel: Merge and cleanup more AMDGPU call lowering code 2021-03-02 17:31:13 -05:00
AMDGPUCallingConv.td [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
AMDGPUCodeGenPrepare.cpp AMDGPU: Use more accurate fast f64 fdiv 2021-01-21 10:51:36 -05:00
AMDGPUCombine.td Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect 2021-03-05 11:05:37 +01:00
AMDGPUExportClustering.cpp [AMDGPU][MC] Refactored exp tgt handling 2021-01-26 14:54:15 +03:00
AMDGPUExportClustering.h [llvm] Add missing header guards (NFC) 2021-01-30 09:53:42 -08:00
AMDGPUFeatures.td
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AMDGPUFixFunctionBitcasts.cpp
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AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGISel.td [AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns 2021-03-18 14:36:04 -07:00
AMDGPUGenRegisterBankInfo.def AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping 2020-08-17 09:53:26 -04:00
AMDGPUGlobalISelUtils.cpp [AMDGPU][GlobalISel] Handle G_PTR_ADD when looking for constant offset 2021-01-28 11:20:09 +01:00
AMDGPUGlobalISelUtils.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUHSAMetadataStreamer.cpp AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPUHSAMetadataStreamer.h AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPUISelDAGToDAG.cpp [AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns 2021-03-18 14:36:04 -07:00
AMDGPUISelLowering.cpp [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
AMDGPUISelLowering.h [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
AMDGPUInstCombineIntrinsic.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPUInstrInfo.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUInstrInfo.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUInstrInfo.td [AMDGPU]: Fixes an invalid clamp selection pattern. 2021-02-08 13:06:30 +01:00
AMDGPUInstructionSelector.cpp [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
AMDGPUInstructionSelector.h [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
AMDGPUInstructions.td [AMDGPU] Inline FSHRPattern into its only use. NFC. 2021-03-26 09:32:02 +00:00
AMDGPULateCodeGenPrepare.cpp [OpaquePtrs] Remove some uses of type-less CreateLoad APIs (NFC) 2021-03-11 14:40:57 +01:00
AMDGPULegalizerInfo.cpp AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPULegalizerInfo.h AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPULibCalls.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPULibFunc.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPULibFunc.h
…
AMDGPULowerIntrinsics.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPULowerKernelArguments.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPULowerKernelAttributes.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPULowerModuleLDSPass.cpp [amdgpu] Implement lower function LDS pass 2021-03-15 15:24:01 +00:00
AMDGPUMCInstLower.cpp [AMDGPU] Remove SI_MASK_BRANCH 2021-03-09 09:13:23 +08:00
AMDGPUMIRFormatter.cpp [AMDGPU] Implement mir parseCustomPseudoSourceValue 2021-01-22 11:24:08 +01:00
AMDGPUMIRFormatter.h [AMDGPU] Implement mir parseCustomPseudoSourceValue 2021-01-22 11:24:08 +01:00
AMDGPUMachineCFGStructurizer.cpp [AMDGPU] Fix build breakage 2021-02-14 09:02:55 -08:00
AMDGPUMachineFunction.cpp [amdgpu] Implement lower function LDS pass 2021-03-15 15:24:01 +00:00
AMDGPUMachineFunction.h [amdgpu] Implement lower function LDS pass 2021-03-15 15:24:01 +00:00
AMDGPUMachineModuleInfo.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUMachineModuleInfo.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUMacroFusion.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPUMacroFusion.h [llvm] Add missing header guards (NFC) 2021-01-30 09:53:42 -08:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUPTNote.h AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
AMDGPUPerfHintAnalysis.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUPerfHintAnalysis.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUPostLegalizerCombiner.cpp Fixed includes. 2021-02-02 09:14:54 +01:00
AMDGPUPreLegalizerCombiner.cpp AMDGPU/GlobalISel: Enable CSE in pre-legalizer combiner 2021-03-21 10:07:37 -04:00
AMDGPUPrintfRuntimeBinding.cpp AMDGPUPrintfRuntimeBinding - don't dereference a dyn_cast<> pointer. NFCI. 2021-01-28 12:38:44 +00:00
AMDGPUPromoteAlloca.cpp [amdgpu] Implement lower function LDS pass 2021-03-15 15:24:01 +00:00
AMDGPUPropagateAttributes.cpp Revert "[IndirectFunctions] Skip propagating attributes to address taken functions" 2021-01-25 15:58:06 -05:00
AMDGPURegBankCombiner.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPURegisterBankInfo.cpp [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
AMDGPURegisterBankInfo.h [AMDGPU][GlobalISel] Use scalar min/max instructions 2021-02-04 17:04:32 +00:00
AMDGPURegisterBanks.td AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank 2020-07-28 16:49:55 -04:00
AMDGPURewriteOutArguments.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUSearchableTables.td [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
AMDGPUSubtarget.cpp [AMDGPU] Split dot2-insts feature 2021-03-17 09:42:21 +00:00
AMDGPUSubtarget.h [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
AMDGPUTargetMachine.cpp [AMDGPU] Rename SIInsertSkips Pass 2021-03-20 11:48:04 +09:00
AMDGPUTargetMachine.h [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDGPUTargetObjectFile.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDGPUTargetObjectFile.h
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AMDGPUTargetTransformInfo.cpp [TTI] Return a TypeSize from getRegisterBitWidth. 2021-03-24 14:45:13 +00:00
AMDGPUTargetTransformInfo.h [TTI] Return a TypeSize from getRegisterBitWidth. 2021-03-24 14:45:13 +00:00
AMDGPUUnifyDivergentExitNodes.cpp [llvm] Populate SmallVector at construction time (NFC) 2021-01-28 22:21:14 -08:00
AMDGPUUnifyMetadata.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
AMDILCFGStructurizer.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
AMDKernelCodeT.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
BUFInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
CMakeLists.txt [AMDGPU] Rename SIInsertSkips Pass 2021-03-20 11:48:04 +09:00
CaymanInstructions.td [AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM 2020-07-08 19:14:49 +01:00
DSInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
EXPInstructions.td [AMDGPU] Separate out real exp instructions by subtarget. NFC. 2020-11-11 17:13:40 +00:00
EvergreenInstructions.td [AMDGPU] Inline FSHRPattern into its only use. NFC. 2021-03-26 09:32:02 +00:00
FLATInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
GCNDPPCombine.cpp [AMDGPU] Refactor DPPCombine 2021-03-23 11:53:53 -04:00
GCNHazardRecognizer.cpp [AMDGPU] Don't check for VMEM hazards on GFX10 2021-03-04 21:44:56 +00:00
GCNHazardRecognizer.h [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
GCNILPSched.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
GCNIterativeScheduler.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
GCNIterativeScheduler.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
GCNMinRegStrategy.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
GCNNSAReassign.cpp [AMDGPU] Do not reassign spilled registers 2021-01-27 16:29:05 -08:00
GCNProcessors.td [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
GCNRegBankReassign.cpp [AMDGPU] Set threshold for regbanks reassign pass 2021-02-23 10:22:31 -08:00
GCNRegPressure.cpp [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
GCNRegPressure.h [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
GCNSchedStrategy.cpp [AMDGPU] Avoid second rescheduling for some regions 2021-02-26 12:29:37 -08:00
GCNSchedStrategy.h [AMDGPU] Avoid second rescheduling for some regions 2021-02-26 12:29:37 -08:00
GCNSubtarget.h [AMDGPU] Use reductions instead of scans in the atomic optimizer 2021-03-26 15:38:14 +00:00
InstCombineTables.td [InstCombine] Move target-specific inst combining 2020-07-22 15:59:49 +02:00
MIMGInstructions.td [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
R600.td
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R600AsmPrinter.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600AsmPrinter.h
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R600ClauseMergePass.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600ControlFlowFinalizer.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600Defines.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
R600EmitClauseMarkers.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600ExpandSpecialInstrs.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600FrameLowering.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600FrameLowering.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
R600ISelLowering.cpp [NFC] Simplify expression 2021-02-05 10:17:02 +00:00
R600ISelLowering.h [TargetLowering] Use Align in allowsMisalignedMemoryAccesses. 2021-02-04 19:22:06 -08:00
R600InstrFormats.td
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R600InstrInfo.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600InstrInfo.h Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate 2020-10-21 11:52:47 +01:00
R600Instructions.td [NFC] Remove unused GetUnderlyingObject paramenter 2020-07-31 02:10:03 -07:00
R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600MachineScheduler.h [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
R600OpenCLImageTypeLoweringPass.cpp TransformUtils: Fix metadata handling in CloneModule (and improve CloneFunctionInto) 2021-02-15 11:56:00 -08:00
R600OptimizeVectorRegisters.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600Packetizer.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600Processors.td
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R600RegisterInfo.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R600RegisterInfo.h [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
R600RegisterInfo.td
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R600Schedule.td
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R600Subtarget.h [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
R700Instructions.td
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SIAddIMGInit.cpp [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
SIAnnotateControlFlow.cpp [AMDGPU] Do not annotate an else branch if there is a kill 2021-03-12 11:52:08 +09:00
SIDefines.h [AMDGPU] Use reductions instead of scans in the atomic optimizer 2021-03-26 15:38:14 +00:00
SIFixSGPRCopies.cpp [AMDGPU] Introduce Strict WQM mode 2021-03-03 14:19:16 +01:00
SIFixVGPRCopies.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
SIFoldOperands.cpp [AMDGPU] Fix "Sequence" spelling. NFC. 2021-03-29 12:11:36 -07:00
SIFormMemoryClauses.cpp AMDGPU: Use kill instruction to hint soft clause live ranges 2021-02-26 18:26:40 -05:00
SIFrameLowering.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
SIFrameLowering.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
SIISelLowering.cpp AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
SIISelLowering.h AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
SIInsertHardClauses.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
SIInsertWaitcnts.cpp [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
SIInstrFormats.td [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
SIInstrInfo.cpp [AMDGPU] Fix copyPhysReg to not produce unalined vgpr access 2021-03-15 14:14:30 -07:00
SIInstrInfo.h [AMDGPU] Better codegen for i64 bitreverse 2021-02-26 15:51:36 +00:00
SIInstrInfo.td AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
SIInstructions.td AMDGPU: Fix allowing immediates for tail call pseudo. 2021-03-21 13:14:04 -04:00
SILateBranchLowering.cpp [AMDGPU] Add MDT update missing from D98915 2021-03-20 13:38:58 +09:00
SILoadStoreOptimizer.cpp [AMDGPU] Fixed msan failure with uninitialized value 2021-03-15 13:58:19 -07:00
SILowerControlFlow.cpp [AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic 2021-02-15 08:45:46 +09:00
SILowerI1Copies.cpp [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
SILowerSGPRSpills.cpp [AMDGPU] Free reserved VGPR if no SGPR spill 2021-03-12 08:11:14 +08:00
SIMachineFunctionInfo.cpp [AMDGPU] Save all lanes for reserved VGPRs 2021-02-04 09:56:36 +01:00
SIMachineFunctionInfo.h [AMDGPU] Implement mir parseCustomPseudoSourceValue 2021-01-22 11:24:08 +01:00
SIMachineScheduler.cpp [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
SIMachineScheduler.h [NFC][AMDGPU] Reduce include files dependency. 2021-01-07 22:22:05 +03:00
SIMemoryLegalizer.cpp [AMDGPU] Only unbundle memory accesses in SIMemoryLegalizer 2021-03-23 11:30:36 +09:00
SIModeRegister.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
SIOptimizeExecMasking.cpp [AMDGPU] Move kill lowering to WQM pass and add live mask tracking 2021-02-11 20:31:29 +09:00
SIOptimizeExecMaskingPreRA.cpp [AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy 2021-03-24 14:14:13 +03:00
SIPeepholeSDWA.cpp [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 2021-01-20 22:22:45 +03:00
SIPostRABundler.cpp AMDGPU: Use kill instruction to hint soft clause live ranges 2021-02-26 18:26:40 -05:00
SIPreAllocateWWMRegs.cpp [AMDGPU] Introduce Strict WQM mode 2021-03-03 14:19:16 +01:00
SIPreEmitPeephole.cpp [AMDGPU] Rename SIInsertSkips Pass 2021-03-20 11:48:04 +09:00
SIProgramInfo.cpp [AMDGPU] Set rsrc1 flags for graphics shaders 2020-11-04 12:25:41 +01:00
SIProgramInfo.h [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
SIRegisterInfo.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
SIRegisterInfo.h [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
SIRegisterInfo.td AMDGPU: Add even aligned VGPR/AGPR register classes 2021-02-24 14:49:37 -05:00
SISchedule.td [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
SIShrinkInstructions.cpp [AMDGPU] Avoid an illegal operand in si-shrink-instructions 2021-01-28 08:49:21 +01:00
SIWholeQuadMode.cpp [AMDGPU] Avoid unnecessary graph visits during WQM marking 2021-03-18 10:00:41 +09:00
SMInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
SOPInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
VIInstrFormats.td
…
VOP1Instructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
VOP2Instructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
VOP3Instructions.td Revert "[AMDGPU] Mark additional VOP3 as commutable" 2021-03-29 14:48:11 -04:00
VOP3PInstructions.td [AMDGPU] Split dot2-insts feature 2021-03-17 09:42:21 +00:00
VOPCInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
VOPInstructions.td [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00