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llvm-project/llvm/lib/Target/Hexagon
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Tomas Matheson a9968c0a33 [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 
Currently needsStackRealignment returns false if canRealignStack returns false.
This means that the behavior of needsStackRealignment does not correspond to
it's name and description; a function might need stack realignment, but if it
is not possible then this function returns false. Furthermore,
needsStackRealignment is not virtual and therefore some backends have made use
of canRealignStack to indicate whether a function needs stack realignment.

This patch attempts to clarify the situation by separating them and introducing
new names:

 - shouldRealignStack - true if there is any reason the stack should be
   realigned

 - canRealignStack - true if we are still able to realign the stack (e.g. we
   can still reserve/have reserved a frame pointer)

 - hasStackRealignment = shouldRealignStack && canRealignStack (not target
   customisable)

Targets can now override shouldRealignStack to indicate that stack realignment
is required.

This change will make it easier in a future change to handle the case where we
need to realign the stack but can't do so (for example when the register
allocator creates an aligned spill after the frame pointer has been
eliminated).

Differential Revision: https://reviews.llvm.org/D98716

Change-Id: Ib9a4d21728bf9d08a545b4365418d3ffe1af4d87
 		2021-03-30 17:31:39 +01:00
..
AsmParser [llvm] Use llvm::erase_value and llvm::erase_if (NFC) 2021-01-02 09:24:15 -08:00
Disassembler llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
MCTargetDesc [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
BitTracker.cpp [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
BitTracker.h [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
CMakeLists.txt [Hexagon] Realign HVX vectors wherever possible 2020-12-09 17:11:25 -06:00
Hexagon.h Hexagon.h - remove unnecessary includes. NFCI. 2020-09-10 16:59:43 +01:00
Hexagon.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonArch.h
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HexagonAsmPrinter.cpp
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HexagonAsmPrinter.h
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HexagonBitSimplify.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonBitTracker.cpp [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
HexagonBitTracker.h [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
HexagonBlockRanges.cpp [llvm] Use llvm::sort (NFC) 2021-01-17 10:39:45 -08:00
HexagonBlockRanges.h [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonBranchRelaxation.cpp
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HexagonCFGOptimizer.cpp Hexagon.h - remove unnecessary includes. NFCI. 2020-09-10 16:59:43 +01:00
HexagonCallingConv.td
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HexagonCommonGEP.cpp [Target] Use llvm::append_range (NFC) 2021-01-03 09:57:43 -08:00
HexagonConstExtenders.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonConstPropagation.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonCopyToCombine.cpp Hexagon.h - remove unnecessary includes. NFCI. 2020-09-10 16:59:43 +01:00
HexagonDepArch.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepArch.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepDecoders.inc [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepIICHVX.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepIICScalar.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepITypes.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepITypes.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepInstrFormats.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepInstrInfo.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepMapAsm2Intrin.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepMappings.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepMask.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepOperands.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepTimingClasses.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonEarlyIfConv.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonExpandCondsets.cpp [llvm] Use *::empty (NFC) 2021-01-16 09:40:55 -08:00
HexagonFixupHwLoops.cpp
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HexagonFrameLowering.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
HexagonFrameLowering.h [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
HexagonGenExtract.cpp
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HexagonGenInsert.cpp [Target] Use llvm::erase_if (NFC) 2020-12-20 17:43:22 -08:00
HexagonGenMux.cpp
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HexagonGenPredicate.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonHardwareLoops.cpp [llvm] Use llvm::is_contained (NFC) 2021-02-14 08:36:20 -08:00
HexagonHazardRecognizer.cpp
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HexagonHazardRecognizer.h
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HexagonIICHVX.td
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HexagonIICScalar.td
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HexagonISelDAGToDAG.cpp [SelectionDAG] Use Align/MaybeAlign in calls to getLoad/getStore/getExtLoad/getTruncStore. 2020-09-14 13:54:50 -07:00
HexagonISelDAGToDAG.h
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HexagonISelDAGToDAGHVX.cpp [Hexagon] Handle additional shuffles that can be made perfect 2020-10-29 19:09:00 -05:00
HexagonISelLowering.cpp [Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32. 2021-03-19 10:54:33 -07:00
HexagonISelLowering.h [TargetLowering] Use Align in allowsMisalignedMemoryAccesses. 2021-02-04 19:22:06 -08:00
HexagonISelLoweringHVX.cpp [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
HexagonInstrFormats.td
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HexagonInstrFormatsV60.td
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HexagonInstrFormatsV65.td
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HexagonInstrInfo.cpp Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate 2020-10-21 11:52:47 +01:00
HexagonInstrInfo.h Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate 2020-10-21 11:52:47 +01:00
HexagonIntrinsics.td
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HexagonIntrinsicsV5.td
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HexagonIntrinsicsV60.td [Hexagon] Fix license headers in some .td files, NFC 2020-10-16 10:03:05 -05:00
HexagonLoopIdiomRecognition.cpp Require chained analyses in BasicAA and AAResults to be transitive 2021-01-11 11:50:07 +01:00
HexagonLoopIdiomRecognition.h [Hexagon][NewPM] Port -hexagon-loop-idiom and add to pipeline 2020-11-20 09:34:37 -08:00
HexagonMCInstLower.cpp [MC] Fix memory leak when allocating MCInst with bump allocator 2020-08-03 16:08:26 -07:00
HexagonMachineFunctionInfo.cpp
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HexagonMachineFunctionInfo.h
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HexagonMachineScheduler.cpp
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HexagonMachineScheduler.h
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HexagonMapAsm2IntrinV62.gen.td
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HexagonMapAsm2IntrinV65.gen.td
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HexagonNewValueJump.cpp
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HexagonOperands.td
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HexagonOptAddrMode.cpp [RDF] Remove uses of RDFRegisters::normalize (deprecate) 2020-08-04 17:02:12 -05:00
HexagonOptimizeSZextends.cpp Hexagon.h - remove unnecessary includes. NFCI. 2020-09-10 16:59:43 +01:00
HexagonPatterns.td [Hexagon] Fix multiclass template parameter types. NFC. 2021-02-06 15:28:26 +00:00
HexagonPatternsHVX.td [Hexagon] Add more patterns for HVX loads and stores 2021-03-17 21:01:52 -05:00
HexagonPatternsV65.td
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HexagonPeephole.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonPseudo.td
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HexagonRDFOpt.cpp
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HexagonRegisterInfo.cpp [Hexagon] Limit virtual register reuse range in FI elimination 2021-03-25 13:59:36 -05:00
HexagonRegisterInfo.h
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HexagonRegisterInfo.td
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HexagonSchedule.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonScheduleV5.td
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HexagonScheduleV55.td
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HexagonScheduleV60.td
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HexagonScheduleV62.td
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HexagonScheduleV65.td
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HexagonScheduleV66.td
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HexagonScheduleV67.td
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HexagonScheduleV67T.td
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HexagonScheduleV68.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonSelectionDAGInfo.cpp
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HexagonSelectionDAGInfo.h
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HexagonSplitConst32AndConst64.cpp
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HexagonSplitDouble.cpp [llvm] Use append_range (NFC) 2021-01-27 23:25:41 -08:00
HexagonStoreWidening.cpp
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HexagonSubtarget.cpp [llvm] Use llvm::find (NFC) 2021-01-19 20:19:14 -08:00
HexagonSubtarget.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonTargetMachine.cpp [llvm] Use Optional::getValueOr (NFC) 2021-01-12 21:43:50 -08:00
HexagonTargetMachine.h [NPM] Add target specific hook to add passes for New Pass Manager 2020-09-30 13:29:43 -07:00
HexagonTargetObjectFile.cpp [X86][AMX] Fix compilation warning introduced by 981a0bd8. 2020-12-30 22:22:13 +08:00
HexagonTargetObjectFile.h
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HexagonTargetStreamer.h
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HexagonTargetTransformInfo.cpp [TTI] Return a TypeSize from getRegisterBitWidth. 2021-03-24 14:45:13 +00:00
HexagonTargetTransformInfo.h [TTI] Return a TypeSize from getRegisterBitWidth. 2021-03-24 14:45:13 +00:00
HexagonVExtract.cpp
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HexagonVLIWPacketizer.cpp
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HexagonVLIWPacketizer.h
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HexagonVectorCombine.cpp [Hexagon] Fix segment start to adjust for gaps between segments 2021-01-19 12:49:39 -06:00
HexagonVectorLoopCarriedReuse.cpp [Hexagon] Make HexagonVLCR compatibile with New PM 2020-09-21 13:45:12 -07:00
HexagonVectorLoopCarriedReuse.h [Hexagon] Make HexagonVLCR compatibile with New PM 2020-09-21 13:45:12 -07:00
HexagonVectorPrint.cpp
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RDFCopy.cpp
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RDFCopy.h
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RDFDeadCode.cpp [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
RDFDeadCode.h
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