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llvm-project/llvm/lib/Target/RISCV
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Craig Topper a33fcafaf0 [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not. 
Without Zfh the half type isn't legal, but it could still be
used as an argument/return in IR. Clang will not generate this today.

Previously we promoted the half value to float for arguments and
returns if the F extension is enabled but Zfh isn't. Then depending on
which ABI is enabled we would pass it in either an FPR or a GPR in
float format.

If the F extension isn't enabled, it would get passed in the lower
16 bits of a GPR in half format.

With this patch the value will always in half format and will be
in the lower bits of a GPR or FPR. This should be consistent
with where the bits are located when Zfh is enabled.

I've based this implementation off of how this is done on ARM.

I've manually nan-boxed the value to 32 bits using integer ops.
It looks like flw, fsw, fmv.s, fmv.w.x, fmf.x.w won't
canonicalize nans so should leave the value alone. I think those
are the instructions that could get used on this value.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D98670
 		2021-03-30 09:47:54 -07:00
..
AsmParser [RISCV] Change parseVTypeI function 2021-02-12 19:38:34 +08:00
Disassembler [RISCV] Fix shared libs build 2021-02-09 06:14:25 -06:00
MCTargetDesc Add missing cases in RISCVMCExpr::getVariantKindName 2021-03-25 12:57:05 +07:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
CMakeLists.txt [RISCV] Merge Utils library into MCTargetDesc 2021-01-14 11:47:30 -08:00
RISCV.h [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCV.td [RISCV] Fix name of Zba extension (NFC) 2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCVCallLowering.cpp [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallLowering.h [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
…
RISCVCleanupVSETVLI.cpp [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli 2021-02-25 07:51:19 -08:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVFrameLowering.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
RISCVFrameLowering.h [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
RISCVISelDAGToDAG.cpp [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register. 2021-03-29 10:20:43 -07:00
RISCVISelDAGToDAG.h [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff). 2021-03-25 09:03:25 -07:00
RISCVISelLowering.cpp [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not. 2021-03-30 09:47:54 -07:00
RISCVISelLowering.h [RISCV] Add support for fixed vector masked gather/scatter. 2021-03-22 10:17:30 -07:00
RISCVInstrFormats.td [RISCV] Make scalable vector FMA commutable for register allocation. 2021-02-08 10:05:33 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVInstrInfo.h [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVInstrInfo.td [RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3. 2021-03-25 23:31:01 -07:00
RISCVInstrInfoA.td [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode. 2021-03-08 09:06:56 -08:00
RISCVInstrInfoB.td [RISCV] Add scheduler classes for the Zba and Zbb extensions. 2021-03-26 14:15:29 -07:00
RISCVInstrInfoC.td [RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg. 2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVInstrInfoF.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVInstrInfoM.td [RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation 2021-03-27 15:37:18 -07:00
RISCVInstrInfoV.td [RISCV] Add vfabs.v pseudo instruction. 2021-03-28 10:24:05 +08:00
RISCVInstrInfoVPseudos.td [RISCV] Add constraint for RVV indexed loads. 2021-03-26 07:23:24 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Lower scalable vector masked loads to intrinsics to match fixed vectors and reduce isel patterns. 2021-03-19 10:39:35 -07:00
RISCVInstrInfoVVLPatterns.td [RISCV] Optimize INSERT_VECTOR_ELT sequences 2021-03-12 09:13:38 +00:00
RISCVInstrInfoZfh.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVInstructionSelector.cpp RISCV: Avoid GlobalISel build break in a future patch 2020-07-13 14:01:57 -04:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMCInstLower.cpp [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCVMachineFunctionInfo.h [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
RISCVMergeBaseOffset.cpp [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
…
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp [RISCV] remove redundant instruction when eliminate frame index 2021-03-21 18:54:00 +08:00
RISCVRegisterInfo.h [RISCV] Improve register allocation around vector masks 2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td [RISCV] Support inline asm for vector instructions. 2021-03-15 11:02:18 +08:00
RISCVSchedRocket.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVSchedSiFive7.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVSchedule.td [RISCV] Move scheduling resources for B into a separate file (NFC) 2021-03-29 20:37:22 -05:00
RISCVScheduleB.td [RISCV] Move scheduling resources for B into a separate file (NFC) 2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp [RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple. 2021-03-14 17:21:31 -07:00
RISCVSubtarget.h [RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other. 2021-02-09 10:47:23 -08:00
RISCVSystemOperands.td [RISCV] Enable the use of the old mucounteren name 2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. 2021-03-02 12:55:51 -08:00
RISCVTargetMachine.h [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. 2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects 2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp [RISCV] Reorder checks in RISCVTTIImpl::getGatherScatterOpCost to avoid calling getMinRVVVectorSizeInBits() when V extension is not enabled. 2021-03-25 14:20:47 -07:00
RISCVTargetTransformInfo.h [RISCV] Add basic cost modelling for fixed vector gather/scatter. 2021-03-24 11:14:14 -07:00