143 lines
4.1 KiB
LLVM
143 lines
4.1 KiB
LLVM
; Test v8i16 absolute.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test with slt.
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define <8 x i16> @f1(<8 x i16> %val) {
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; CHECK-LABEL: f1:
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; CHECK: vlph %v24, %v24
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; CHECK: br %r14
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%cmp = icmp slt <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
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ret <8 x i16> %ret
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}
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; Test with sle.
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define <8 x i16> @f2(<8 x i16> %val) {
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; CHECK-LABEL: f2:
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; CHECK: vlph %v24, %v24
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; CHECK: br %r14
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%cmp = icmp sle <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
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ret <8 x i16> %ret
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}
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; Test with sgt.
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define <8 x i16> @f3(<8 x i16> %val) {
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; CHECK-LABEL: f3:
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; CHECK: vlph %v24, %v24
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; CHECK: br %r14
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%cmp = icmp sgt <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
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ret <8 x i16> %ret
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}
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; Test with sge.
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define <8 x i16> @f4(<8 x i16> %val) {
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; CHECK-LABEL: f4:
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; CHECK: vlph %v24, %v24
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; CHECK: br %r14
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%cmp = icmp sge <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
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ret <8 x i16> %ret
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}
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; Test that negative absolute uses VLPH too. There is no vector equivalent
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; of LOAD NEGATIVE.
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define <8 x i16> @f5(<8 x i16> %val) {
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; CHECK-LABEL: f5:
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; CHECK: vlph [[REG:%v[0-9]+]], %v24
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; CHECK: vlch %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp slt <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%abs = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
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%ret = sub <8 x i16> zeroinitializer, %abs
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ret <8 x i16> %ret
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}
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; Try another form of negative absolute (slt version).
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define <8 x i16> @f6(<8 x i16> %val) {
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; CHECK-LABEL: f6:
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; CHECK: vlph [[REG:%v[0-9]+]], %v24
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; CHECK: vlch %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp slt <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
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ret <8 x i16> %ret
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}
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; Test with sle.
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define <8 x i16> @f7(<8 x i16> %val) {
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; CHECK-LABEL: f7:
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; CHECK: vlph [[REG:%v[0-9]+]], %v24
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; CHECK: vlch %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp sle <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
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ret <8 x i16> %ret
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}
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; Test with sgt.
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define <8 x i16> @f8(<8 x i16> %val) {
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; CHECK-LABEL: f8:
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; CHECK: vlph [[REG:%v[0-9]+]], %v24
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; CHECK: vlch %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp sgt <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
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ret <8 x i16> %ret
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}
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; Test with sge.
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define <8 x i16> @f9(<8 x i16> %val) {
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; CHECK-LABEL: f9:
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; CHECK: vlph [[REG:%v[0-9]+]], %v24
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; CHECK: vlch %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp sge <8 x i16> %val, zeroinitializer
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%neg = sub <8 x i16> zeroinitializer, %val
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%ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
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ret <8 x i16> %ret
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}
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; Test with an SRA-based boolean vector.
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define <8 x i16> @f10(<8 x i16> %val) {
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; CHECK-LABEL: f10:
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; CHECK: vlph %v24, %v24
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; CHECK: br %r14
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%shr = ashr <8 x i16> %val,
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<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%neg = sub <8 x i16> zeroinitializer, %val
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%and1 = and <8 x i16> %shr, %neg
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%not = xor <8 x i16> %shr,
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<i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%and2 = and <8 x i16> %not, %val
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%ret = or <8 x i16> %and1, %and2
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ret <8 x i16> %ret
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}
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; ...and again in reverse
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define <8 x i16> @f11(<8 x i16> %val) {
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; CHECK-LABEL: f11:
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; CHECK: vlph [[REG:%v[0-9]+]], %v24
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; CHECK: vlch %v24, [[REG]]
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; CHECK: br %r14
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%shr = ashr <8 x i16> %val,
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<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%and1 = and <8 x i16> %shr, %val
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%not = xor <8 x i16> %shr,
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<i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%neg = sub <8 x i16> zeroinitializer, %val
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%and2 = and <8 x i16> %not, %neg
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%ret = or <8 x i16> %and1, %and2
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ret <8 x i16> %ret
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}
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