570 lines
17 KiB
C++
570 lines
17 KiB
C++
//===-- DNBArchImpl.cpp -----------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Created by Greg Clayton on 6/25/07.
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//
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//===----------------------------------------------------------------------===//
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#if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
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#if __DARWIN_UNIX03
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#define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) __##reg
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#else
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#define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) reg
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#endif
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#include "MacOSX/ppc/DNBArchImpl.h"
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#include "MacOSX/MachThread.h"
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#include "DNBBreakpoint.h"
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#include "DNBLog.h"
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#include "DNBRegisterInfo.h"
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static const uint8_t g_breakpoint_opcode[] = { 0x7F, 0xC0, 0x00, 0x08 };
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const uint8_t * const
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DNBArchMachPPC::SoftwareBreakpointOpcode (nub_size_t size)
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{
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if (size == 4)
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return g_breakpoint_opcode;
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return NULL;
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}
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uint32_t
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DNBArchMachPPC::GetCPUType()
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{
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return CPU_TYPE_POWERPC;
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}
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uint64_t
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DNBArchMachPPC::GetPC(uint64_t failValue)
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{
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// Get program counter
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if (GetGPRState(false) == KERN_SUCCESS)
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return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0);
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return failValue;
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}
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kern_return_t
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DNBArchMachPPC::SetPC(uint64_t value)
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{
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// Get program counter
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kern_return_t err = GetGPRState(false);
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if (err == KERN_SUCCESS)
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{
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m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0) = value;
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err = SetGPRState();
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}
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return err == KERN_SUCCESS;
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}
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uint64_t
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DNBArchMachPPC::GetSP(uint64_t failValue)
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{
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// Get stack pointer
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if (GetGPRState(false) == KERN_SUCCESS)
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return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(r1);
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return failValue;
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}
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kern_return_t
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DNBArchMachPPC::GetGPRState(bool force)
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{
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if (force || m_state.GetError(e_regSetGPR, Read))
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{
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mach_msg_type_number_t count = e_regSetWordSizeGPR;
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m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetGPR, (thread_state_t)&m_state.gpr, &count));
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}
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return m_state.GetError(e_regSetGPR, Read);
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}
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kern_return_t
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DNBArchMachPPC::GetFPRState(bool force)
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{
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if (force || m_state.GetError(e_regSetFPR, Read))
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{
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mach_msg_type_number_t count = e_regSetWordSizeFPR;
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m_state.SetError(e_regSetFPR, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetFPR, (thread_state_t)&m_state.fpr, &count));
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}
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return m_state.GetError(e_regSetFPR, Read);
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}
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kern_return_t
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DNBArchMachPPC::GetEXCState(bool force)
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{
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if (force || m_state.GetError(e_regSetEXC, Read))
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{
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mach_msg_type_number_t count = e_regSetWordSizeEXC;
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m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetEXC, (thread_state_t)&m_state.exc, &count));
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}
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return m_state.GetError(e_regSetEXC, Read);
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}
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kern_return_t
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DNBArchMachPPC::GetVECState(bool force)
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{
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if (force || m_state.GetError(e_regSetVEC, Read))
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{
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mach_msg_type_number_t count = e_regSetWordSizeVEC;
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m_state.SetError(e_regSetVEC, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetVEC, (thread_state_t)&m_state.vec, &count));
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}
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return m_state.GetError(e_regSetVEC, Read);
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}
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kern_return_t
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DNBArchMachPPC::SetGPRState()
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{
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m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetGPR, (thread_state_t)&m_state.gpr, e_regSetWordSizeGPR));
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return m_state.GetError(e_regSetGPR, Write);
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}
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kern_return_t
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DNBArchMachPPC::SetFPRState()
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{
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m_state.SetError(e_regSetFPR, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetFPR, (thread_state_t)&m_state.fpr, e_regSetWordSizeFPR));
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return m_state.GetError(e_regSetFPR, Write);
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}
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kern_return_t
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DNBArchMachPPC::SetEXCState()
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{
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m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetEXC, (thread_state_t)&m_state.exc, e_regSetWordSizeEXC));
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return m_state.GetError(e_regSetEXC, Write);
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}
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kern_return_t
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DNBArchMachPPC::SetVECState()
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{
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m_state.SetError(e_regSetVEC, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetVEC, (thread_state_t)&m_state.vec, e_regSetWordSizeVEC));
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return m_state.GetError(e_regSetVEC, Write);
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}
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bool
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DNBArchMachPPC::ThreadWillResume()
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{
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bool success = true;
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// Do we need to step this thread? If so, let the mach thread tell us so.
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if (m_thread->IsStepping())
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{
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// This is the primary thread, let the arch do anything it needs
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success = EnableHardwareSingleStep(true) == KERN_SUCCESS;
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}
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return success;
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}
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bool
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DNBArchMachPPC::ThreadDidStop()
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{
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bool success = true;
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m_state.InvalidateAllRegisterStates();
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// Are we stepping a single instruction?
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if (GetGPRState(true) == KERN_SUCCESS)
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{
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// We are single stepping, was this the primary thread?
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if (m_thread->IsStepping())
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{
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// This was the primary thread, we need to clear the trace
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// bit if so.
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success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
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}
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else
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{
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// The MachThread will automatically restore the suspend count
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// in ThreadDidStop(), so we don't need to do anything here if
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// we weren't the primary thread the last time
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}
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}
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return success;
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}
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// Set the single step bit in the processor status register.
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kern_return_t
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DNBArchMachPPC::EnableHardwareSingleStep (bool enable)
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{
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DNBLogThreadedIf(LOG_STEP, "DNBArchMachPPC::EnableHardwareSingleStep( enable = %d )", enable);
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if (GetGPRState(false) == KERN_SUCCESS)
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{
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const uint32_t trace_bit = 0x400;
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if (enable)
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m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) |= trace_bit;
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else
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m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) &= ~trace_bit;
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return SetGPRState();
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}
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return m_state.GetError(e_regSetGPR, Read);
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}
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//----------------------------------------------------------------------
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// Register information defintions for 32 bit PowerPC.
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//----------------------------------------------------------------------
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enum gpr_regnums
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{
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e_regNumGPR_srr0,
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e_regNumGPR_srr1,
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e_regNumGPR_r0,
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e_regNumGPR_r1,
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e_regNumGPR_r2,
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e_regNumGPR_r3,
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e_regNumGPR_r4,
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e_regNumGPR_r5,
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e_regNumGPR_r6,
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e_regNumGPR_r7,
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e_regNumGPR_r8,
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e_regNumGPR_r9,
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e_regNumGPR_r10,
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e_regNumGPR_r11,
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e_regNumGPR_r12,
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e_regNumGPR_r13,
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e_regNumGPR_r14,
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e_regNumGPR_r15,
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e_regNumGPR_r16,
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e_regNumGPR_r17,
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e_regNumGPR_r18,
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e_regNumGPR_r19,
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e_regNumGPR_r20,
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e_regNumGPR_r21,
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e_regNumGPR_r22,
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e_regNumGPR_r23,
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e_regNumGPR_r24,
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e_regNumGPR_r25,
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e_regNumGPR_r26,
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e_regNumGPR_r27,
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e_regNumGPR_r28,
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e_regNumGPR_r29,
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e_regNumGPR_r30,
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e_regNumGPR_r31,
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e_regNumGPR_cr,
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e_regNumGPR_xer,
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e_regNumGPR_lr,
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e_regNumGPR_ctr,
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e_regNumGPR_mq,
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e_regNumGPR_vrsave
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};
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// General purpose registers
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static DNBRegisterInfo g_gpr_registers[] =
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{
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{ "srr0" , Uint, 4, Hex },
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{ "srr1" , Uint, 4, Hex },
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{ "r0" , Uint, 4, Hex },
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{ "r1" , Uint, 4, Hex },
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{ "r2" , Uint, 4, Hex },
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{ "r3" , Uint, 4, Hex },
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{ "r4" , Uint, 4, Hex },
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{ "r5" , Uint, 4, Hex },
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{ "r6" , Uint, 4, Hex },
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{ "r7" , Uint, 4, Hex },
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{ "r8" , Uint, 4, Hex },
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{ "r9" , Uint, 4, Hex },
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{ "r10" , Uint, 4, Hex },
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{ "r11" , Uint, 4, Hex },
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{ "r12" , Uint, 4, Hex },
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{ "r13" , Uint, 4, Hex },
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{ "r14" , Uint, 4, Hex },
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{ "r15" , Uint, 4, Hex },
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{ "r16" , Uint, 4, Hex },
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{ "r17" , Uint, 4, Hex },
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{ "r18" , Uint, 4, Hex },
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{ "r19" , Uint, 4, Hex },
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{ "r20" , Uint, 4, Hex },
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{ "r21" , Uint, 4, Hex },
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{ "r22" , Uint, 4, Hex },
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{ "r23" , Uint, 4, Hex },
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{ "r24" , Uint, 4, Hex },
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{ "r25" , Uint, 4, Hex },
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{ "r26" , Uint, 4, Hex },
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{ "r27" , Uint, 4, Hex },
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{ "r28" , Uint, 4, Hex },
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{ "r29" , Uint, 4, Hex },
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{ "r30" , Uint, 4, Hex },
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{ "r31" , Uint, 4, Hex },
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{ "cr" , Uint, 4, Hex },
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{ "xer" , Uint, 4, Hex },
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{ "lr" , Uint, 4, Hex },
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{ "ctr" , Uint, 4, Hex },
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{ "mq" , Uint, 4, Hex },
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{ "vrsave", Uint, 4, Hex },
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};
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// Floating point registers
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static DNBRegisterInfo g_fpr_registers[] =
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{
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{ "fp0" , IEEE754, 8, Float },
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{ "fp1" , IEEE754, 8, Float },
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{ "fp2" , IEEE754, 8, Float },
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{ "fp3" , IEEE754, 8, Float },
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{ "fp4" , IEEE754, 8, Float },
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{ "fp5" , IEEE754, 8, Float },
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{ "fp6" , IEEE754, 8, Float },
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{ "fp7" , IEEE754, 8, Float },
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{ "fp8" , IEEE754, 8, Float },
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{ "fp9" , IEEE754, 8, Float },
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{ "fp10" , IEEE754, 8, Float },
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{ "fp11" , IEEE754, 8, Float },
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{ "fp12" , IEEE754, 8, Float },
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{ "fp13" , IEEE754, 8, Float },
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{ "fp14" , IEEE754, 8, Float },
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{ "fp15" , IEEE754, 8, Float },
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{ "fp16" , IEEE754, 8, Float },
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{ "fp17" , IEEE754, 8, Float },
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{ "fp18" , IEEE754, 8, Float },
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{ "fp19" , IEEE754, 8, Float },
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{ "fp20" , IEEE754, 8, Float },
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{ "fp21" , IEEE754, 8, Float },
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{ "fp22" , IEEE754, 8, Float },
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{ "fp23" , IEEE754, 8, Float },
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{ "fp24" , IEEE754, 8, Float },
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{ "fp25" , IEEE754, 8, Float },
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{ "fp26" , IEEE754, 8, Float },
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{ "fp27" , IEEE754, 8, Float },
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{ "fp28" , IEEE754, 8, Float },
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{ "fp29" , IEEE754, 8, Float },
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{ "fp30" , IEEE754, 8, Float },
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{ "fp31" , IEEE754, 8, Float },
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{ "fpscr" , Uint, 4, Hex }
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};
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// Exception registers
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static DNBRegisterInfo g_exc_registers[] =
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{
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{ "dar" , Uint, 4, Hex },
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{ "dsisr" , Uint, 4, Hex },
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{ "exception" , Uint, 4, Hex }
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};
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// Altivec registers
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static DNBRegisterInfo g_vec_registers[] =
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{
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{ "vr0" , Vector, 16, VectorOfFloat32 },
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{ "vr1" , Vector, 16, VectorOfFloat32 },
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{ "vr2" , Vector, 16, VectorOfFloat32 },
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{ "vr3" , Vector, 16, VectorOfFloat32 },
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{ "vr4" , Vector, 16, VectorOfFloat32 },
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{ "vr5" , Vector, 16, VectorOfFloat32 },
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{ "vr6" , Vector, 16, VectorOfFloat32 },
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{ "vr7" , Vector, 16, VectorOfFloat32 },
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{ "vr8" , Vector, 16, VectorOfFloat32 },
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{ "vr9" , Vector, 16, VectorOfFloat32 },
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{ "vr10" , Vector, 16, VectorOfFloat32 },
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{ "vr11" , Vector, 16, VectorOfFloat32 },
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{ "vr12" , Vector, 16, VectorOfFloat32 },
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{ "vr13" , Vector, 16, VectorOfFloat32 },
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{ "vr14" , Vector, 16, VectorOfFloat32 },
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{ "vr15" , Vector, 16, VectorOfFloat32 },
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{ "vr16" , Vector, 16, VectorOfFloat32 },
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{ "vr17" , Vector, 16, VectorOfFloat32 },
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{ "vr18" , Vector, 16, VectorOfFloat32 },
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{ "vr19" , Vector, 16, VectorOfFloat32 },
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{ "vr20" , Vector, 16, VectorOfFloat32 },
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{ "vr21" , Vector, 16, VectorOfFloat32 },
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{ "vr22" , Vector, 16, VectorOfFloat32 },
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{ "vr23" , Vector, 16, VectorOfFloat32 },
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{ "vr24" , Vector, 16, VectorOfFloat32 },
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{ "vr25" , Vector, 16, VectorOfFloat32 },
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{ "vr26" , Vector, 16, VectorOfFloat32 },
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{ "vr27" , Vector, 16, VectorOfFloat32 },
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{ "vr28" , Vector, 16, VectorOfFloat32 },
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{ "vr29" , Vector, 16, VectorOfFloat32 },
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{ "vr30" , Vector, 16, VectorOfFloat32 },
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{ "vr31" , Vector, 16, VectorOfFloat32 },
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{ "vscr" , Uint, 16, Hex },
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{ "vrvalid" , Uint, 4, Hex }
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};
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// Number of registers in each register set
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const size_t k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo);
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const size_t k_num_fpr_registers = sizeof(g_fpr_registers)/sizeof(DNBRegisterInfo);
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const size_t k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo);
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const size_t k_num_vec_registers = sizeof(g_vec_registers)/sizeof(DNBRegisterInfo);
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// Total number of registers for this architecture
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const size_t k_num_ppc_registers = k_num_gpr_registers + k_num_fpr_registers + k_num_exc_registers + k_num_vec_registers;
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//----------------------------------------------------------------------
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// Register set definitions. The first definitions at register set index
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// of zero is for all registers, followed by other registers sets. The
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// register information for the all register set need not be filled in.
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//----------------------------------------------------------------------
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static const DNBRegisterSetInfo g_reg_sets[] =
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{
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{ "PowerPC Registers", NULL, k_num_ppc_registers },
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{ "General Purpose Registers", g_gpr_registers, k_num_gpr_registers },
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{ "Floating Point Registers", g_fpr_registers, k_num_fpr_registers },
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{ "Exception State Registers", g_exc_registers, k_num_exc_registers },
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{ "Altivec Registers", g_vec_registers, k_num_vec_registers }
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};
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// Total number of register sets for this architecture
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const size_t k_num_register_sets = sizeof(g_reg_sets)/sizeof(DNBRegisterSetInfo);
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const DNBRegisterSetInfo *
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DNBArchMachPPC::GetRegisterSetInfo(nub_size_t *num_reg_sets) const
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{
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*num_reg_sets = k_num_register_sets;
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return g_reg_sets;
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}
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bool
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DNBArchMachPPC::GetRegisterValue(int set, int reg, DNBRegisterValue *value) const
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{
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if (set == REGISTER_SET_GENERIC)
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{
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switch (reg)
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{
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case GENERIC_REGNUM_PC: // Program Counter
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set = e_regSetGPR;
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reg = e_regNumGPR_srr0;
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break;
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case GENERIC_REGNUM_SP: // Stack Pointer
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set = e_regSetGPR;
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reg = e_regNumGPR_r1;
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break;
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case GENERIC_REGNUM_FP: // Frame Pointer
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// Return false for now instead of returning r30 as gcc 3.x would
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// use a variety of registers for the FP and it takes inspecting
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// the stack to make sure there is a frame pointer before we can
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// determine the FP.
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return false;
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case GENERIC_REGNUM_RA: // Return Address
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set = e_regSetGPR;
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reg = e_regNumGPR_lr;
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break;
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case GENERIC_REGNUM_FLAGS: // Processor flags register
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set = e_regSetGPR;
|
|
reg = e_regNumGPR_srr1;
|
|
break;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (!m_state.RegsAreValid(set))
|
|
return false;
|
|
|
|
const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
|
|
if (regInfo)
|
|
{
|
|
value->info = *regInfo;
|
|
switch (set)
|
|
{
|
|
case e_regSetGPR:
|
|
if (reg < k_num_gpr_registers)
|
|
{
|
|
value->value.uint32 = (&m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0))[reg];
|
|
return true;
|
|
}
|
|
break;
|
|
|
|
case e_regSetFPR:
|
|
if (reg < 32)
|
|
{
|
|
value->value.float64 = m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpregs)[reg];
|
|
return true;
|
|
}
|
|
else if (reg == 32)
|
|
{
|
|
value->value.uint32 = m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpscr);
|
|
return true;
|
|
}
|
|
break;
|
|
|
|
case e_regSetEXC:
|
|
if (reg < k_num_exc_registers)
|
|
{
|
|
value->value.uint32 = (&m_state.exc.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(dar))[reg];
|
|
return true;
|
|
}
|
|
break;
|
|
|
|
case e_regSetVEC:
|
|
if (reg < k_num_vec_registers)
|
|
{
|
|
if (reg < 33) // FP0 - FP31 and VSCR
|
|
{
|
|
// Copy all 4 uint32 values for this vector register
|
|
value->value.v_uint32[0] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][0];
|
|
value->value.v_uint32[1] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][1];
|
|
value->value.v_uint32[2] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][2];
|
|
value->value.v_uint32[3] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][3];
|
|
return true;
|
|
}
|
|
else if (reg == 34) // VRVALID
|
|
{
|
|
value->value.uint32 = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vrvalid);
|
|
return true;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
kern_return_t
|
|
DNBArchMachPPC::GetRegisterState(int set, bool force)
|
|
{
|
|
switch (set)
|
|
{
|
|
case e_regSetALL:
|
|
return GetGPRState(force) |
|
|
GetFPRState(force) |
|
|
GetEXCState(force) |
|
|
GetVECState(force);
|
|
case e_regSetGPR: return GetGPRState(force);
|
|
case e_regSetFPR: return GetFPRState(force);
|
|
case e_regSetEXC: return GetEXCState(force);
|
|
case e_regSetVEC: return GetVECState(force);
|
|
default: break;
|
|
}
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
|
|
kern_return_t
|
|
DNBArchMachPPC::SetRegisterState(int set)
|
|
{
|
|
// Make sure we have a valid context to set.
|
|
kern_return_t err = GetRegisterState(set, false);
|
|
if (err != KERN_SUCCESS)
|
|
return err;
|
|
|
|
switch (set)
|
|
{
|
|
case e_regSetALL: return SetGPRState() | SetFPRState() | SetEXCState() | SetVECState();
|
|
case e_regSetGPR: return SetGPRState();
|
|
case e_regSetFPR: return SetFPRState();
|
|
case e_regSetEXC: return SetEXCState();
|
|
case e_regSetVEC: return SetVECState();
|
|
default: break;
|
|
}
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
|
|
bool
|
|
DNBArchMachPPC::RegisterSetStateIsValid (int set) const
|
|
{
|
|
return m_state.RegsAreValid(set);
|
|
}
|
|
|
|
|
|
#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
|
|
|