300 lines
8.8 KiB
C++
300 lines
8.8 KiB
C++
//===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "EmulateInstructionARM.h"
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using namespace lldb;
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using namespace lldb_private;
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// ARM constants used during decoding
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#define REG_RD 0
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#define LDM_REGLIST 1
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#define PC_REG 15
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#define PC_REGLIST_BIT 0x8000
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// ARM conditions
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#define COND_EQ 0x0
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#define COND_NE 0x1
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#define COND_CS 0x2
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#define COND_HS 0x2
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#define COND_CC 0x3
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#define COND_LO 0x3
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#define COND_MI 0x4
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#define COND_PL 0x5
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#define COND_VS 0x6
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#define COND_VC 0x7
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#define COND_HI 0x8
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#define COND_LS 0x9
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#define COND_GE 0xA
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#define COND_LT 0xB
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#define COND_GT 0xC
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#define COND_LE 0xD
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#define COND_AL 0xE
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#define COND_UNCOND 0xF
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#define MASK_CPSR_MODE_MASK (0x0000001fu)
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#define MASK_CPSR_T (1u << 5)
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#define MASK_CPSR_F (1u << 6)
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#define MASK_CPSR_I (1u << 7)
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#define MASK_CPSR_A (1u << 8)
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#define MASK_CPSR_E (1u << 9)
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#define MASK_CPSR_GE_MASK (0x000f0000u)
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#define MASK_CPSR_J (1u << 24)
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#define MASK_CPSR_Q (1u << 27)
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#define MASK_CPSR_V (1u << 28)
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#define MASK_CPSR_C (1u << 29)
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#define MASK_CPSR_Z (1u << 30)
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#define MASK_CPSR_N (1u << 31)
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#define ARMv4 (1u << 0)
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#define ARMv4T (1u << 1)
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#define ARMv5T (1u << 2)
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#define ARMv5TE (1u << 3)
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#define ARMv5TEJ (1u << 4)
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#define ARMv6 (1u << 5)
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#define ARMv6K (1u << 6)
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#define ARMv6T2 (1u << 7)
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#define ARMv7 (1u << 8)
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#define ARMv8 (1u << 8)
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#define ARMvAll (0xffffffffu)
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typedef bool (*EmulateCallback) (EmulateInstructionARM *emulator);
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typedef enum ARMEncoding
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{
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eEncodingA1,
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eEncodingA2,
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eEncodingA3,
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eEncodingA4,
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eEncodingA5,
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eEncodingT1,
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eEncodingT2,
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eEncodingT3,
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eEncodingT4,
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eEncodingT5,
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} ARMEncoding;
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typedef struct ARMOpcode
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{
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uint32_t mask;
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uint32_t value;
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uint32_t variants;
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ARMEncoding encoding;
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const char *name;
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EmulateCallback callback;
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};
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static bool
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EmulateARMPushEncodingA1 (EmulateInstructionARM *emulator)
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{
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#if 0
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// ARM pseudo code...
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if (ConditionPassed())
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{
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EncodingSpecificOperations();
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NullCheckIfThumbEE(13);
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address = SP - 4*BitCount(registers);
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for (i = 0 to 14)
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{
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if (registers<i> == ’1’)
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{
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if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1
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MemA[address,4] = bits(32) UNKNOWN;
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else
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MemA[address,4] = R[i];
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address = address + 4;
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}
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}
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if (registers<15> == ’1’) // Only possible for encoding A1 or A2
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MemA[address,4] = PCStoreValue();
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SP = SP - 4*BitCount(registers);
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}
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#endif
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bool success = false;
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const uint32_t opcode = emulator->OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (emulator->ConditionPassed())
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{
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const uint32_t addr_byte_size = emulator->GetAddressByteSize();
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const addr_t sp = emulator->ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success);
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if (!success)
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return false;
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const uint32_t registers = EmulateInstruction::UnsignedBits (opcode, 15, 0);
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addr_t sp_offset = addr_byte_size * EmulateInstruction::BitCount (registers);
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addr_t addr = sp - sp_offset;
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uint32_t i;
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EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 };
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for (i=0; i<15; ++i)
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{
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if (EmulateInstruction::BitIsSet (registers, 1u << i))
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{
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context.arg1 = dwarf_r0 + i; // arg1 in the context is the DWARF register number
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context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset
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uint32_t reg_value = emulator->ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success);
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if (!success)
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return false;
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if (!emulator->WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size))
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return false;
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addr += addr_byte_size;
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}
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}
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if (EmulateInstruction::BitIsSet (registers, 1u << 15))
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{
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context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number
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context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset
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const uint32_t pc = emulator->ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
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if (!success)
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return false;
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if (!emulator->WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size))
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return false;
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}
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context.type = EmulateInstruction::eContextAdjustStackPointer;
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context.arg0 = eRegisterKindGeneric;
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context.arg1 = LLDB_REGNUM_GENERIC_SP;
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context.arg2 = sp_offset;
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if (!emulator->WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
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return false;
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}
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return true;
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}
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static ARMOpcode g_arm_opcodes[] =
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{
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{ 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, "PUSH<c> <registers>", EmulateARMPushEncodingA1 }
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};
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static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
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bool
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EmulateInstructionARM::ReadInstruction ()
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{
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bool success = false;
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m_inst_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success);
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if (success)
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{
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addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success);
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if (success)
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{
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Context read_inst_context = {eContextReadOpcode, 0, 0};
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if (m_inst_cpsr & MASK_CPSR_T)
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{
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m_inst_mode = eModeThumb;
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uint32_t thumb_opcode = ReadMemoryUnsigned(read_inst_context, pc, 2, 0, &success);
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if (success)
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{
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if ((m_inst.opcode.inst16 & 0xe000) != 0xe000 || ((m_inst.opcode.inst16 & 0x1800u) == 0))
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{
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m_inst.opcode_type = eOpcode16;
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m_inst.opcode.inst16 = thumb_opcode;
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}
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else
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{
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m_inst.opcode_type = eOpcode32;
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m_inst.opcode.inst32 = (thumb_opcode << 16) | ReadMemoryUnsigned(read_inst_context, pc + 2, 2, 0, &success);
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}
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}
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}
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else
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{
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m_inst_mode = eModeARM;
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m_inst.opcode_type = eOpcode32;
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m_inst.opcode.inst32 = ReadMemoryUnsigned(read_inst_context, pc, 4, 0, &success);
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}
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}
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}
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if (!success)
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{
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m_inst_mode = eModeInvalid;
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m_inst_pc = LLDB_INVALID_ADDRESS;
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}
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return success;
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}
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uint32_t
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EmulateInstructionARM::CurrentCond ()
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{
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switch (m_inst_mode)
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{
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default:
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case eModeInvalid:
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break;
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case eModeARM:
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return UnsignedBits(m_inst.opcode.inst32, 31, 28);
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case eModeThumb:
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return 0x0000000Eu; // Return always for now, we need to handl IT instructions later
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}
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return UINT32_MAX; // Return invalid value
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}
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bool
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EmulateInstructionARM::ConditionPassed ()
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{
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if (m_inst_cpsr == 0)
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return false;
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const uint32_t cond = CurrentCond ();
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if (cond == UINT32_MAX)
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return false;
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bool result = false;
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switch (UnsignedBits(cond, 3, 1))
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{
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case 0: result = (m_inst_cpsr & MASK_CPSR_Z) != 0; break;
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case 1: result = (m_inst_cpsr & MASK_CPSR_C) != 0; break;
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case 2: result = (m_inst_cpsr & MASK_CPSR_N) != 0; break;
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case 3: result = (m_inst_cpsr & MASK_CPSR_V) != 0; break;
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case 4: result = ((m_inst_cpsr & MASK_CPSR_C) != 0) && ((m_inst_cpsr & MASK_CPSR_Z) == 0); break;
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case 5:
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{
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bool n = (m_inst_cpsr & MASK_CPSR_N);
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bool v = (m_inst_cpsr & MASK_CPSR_V);
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result = n == v;
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}
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break;
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case 6:
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{
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bool n = (m_inst_cpsr & MASK_CPSR_N);
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bool v = (m_inst_cpsr & MASK_CPSR_V);
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result = n == v && ((m_inst_cpsr & MASK_CPSR_Z) == 0);
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}
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break;
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case 7:
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result = true;
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break;
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}
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if (cond & 1)
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result = !result;
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return result;
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}
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bool
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EmulateInstructionARM::EvaluateInstruction ()
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{
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return false;
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}
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