503 lines
20 KiB
TableGen
503 lines
20 KiB
TableGen
// PC Relative flag (for instructions that use the address of the prefix for
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// address computations).
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class isPCRel { bit PCRel = 1; }
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// Top-level class for prefixed instructions.
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class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin> : Instruction {
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field bits<64> Inst;
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field bits<64> SoftFail = 0;
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bit PCRel = 0; // Default value, set by isPCRel.
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let Size = 8;
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let Namespace = "PPC";
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let OutOperandList = OOL;
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let InOperandList = IOL;
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let AsmString = asmstr;
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let Itinerary = itin;
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let Inst{0-5} = pref;
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let Inst{32-37} = opcode;
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bits<1> PPC970_First = 0;
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bits<1> PPC970_Single = 0;
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bits<1> PPC970_Cracked = 0;
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bits<3> PPC970_Unit = 0;
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/// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
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/// these must be reflected there! See comments there for what these are.
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let TSFlags{0} = PPC970_First;
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let TSFlags{1} = PPC970_Single;
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let TSFlags{2} = PPC970_Cracked;
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let TSFlags{5-3} = PPC970_Unit;
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bits<1> Prefixed = 1; // This is a prefixed instruction.
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let TSFlags{7} = Prefixed;
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// For cases where multiple instruction definitions really represent the
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// same underlying instruction but with one definition for 64-bit arguments
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// and one for 32-bit arguments, this bit breaks the degeneracy between
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// the two forms and allows TableGen to generate mapping tables.
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bit Interpretation64Bit = 0;
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// Fields used for relation models.
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string BaseName = "";
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}
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class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<5> FRS;
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bits<39> D_RA;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 2;
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let Inst{8-10} = 0;
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let Inst{11} = PCRel;
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let Inst{12-13} = 0;
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let Inst{14-31} = D_RA{33-16}; // d0
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// The instruction.
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let Inst{38-42} = FRS{4-0};
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let Inst{43-47} = D_RA{38-34}; // RA
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let Inst{48-63} = D_RA{15-0}; // d1
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}
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class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<5> RT;
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bits<5> RA;
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bits<34> SI;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 2;
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let Inst{8-10} = 0;
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let Inst{11} = PCRel;
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let Inst{12-13} = 0;
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let Inst{14-31} = SI{33-16};
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// The instruction.
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let Inst{38-42} = RT;
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let Inst{43-47} = RA;
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let Inst{48-63} = SI{15-0};
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}
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class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<5> RT;
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bits<34> SI;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 2;
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let Inst{8-10} = 0;
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let Inst{11} = 0;
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let Inst{12-13} = 0;
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let Inst{14-31} = SI{33-16};
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// The instruction.
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let Inst{38-42} = RT;
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let Inst{43-47} = 0;
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let Inst{48-63} = SI{15-0};
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}
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multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>, isPCRel;
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}
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class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<5> RT;
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bits<39> D_RA;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-10} = 0;
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let Inst{11} = PCRel;
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let Inst{12-13} = 0;
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let Inst{14-31} = D_RA{33-16}; // d0
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// The instruction.
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let Inst{38-42} = RT{4-0};
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let Inst{43-47} = D_RA{38-34}; // RA
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let Inst{48-63} = D_RA{15-0}; // d1
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}
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// 8LS:D-Form: [ 1 0 0 // R // d0
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// PO TX T RA d1 ]
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class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<39> D_RA;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 0;
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let Inst{8} = 0;
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let Inst{9-10} = 0; // reserved
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let Inst{11} = PCRel;
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let Inst{12-13} = 0; // reserved
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let Inst{14-31} = D_RA{33-16}; // d0
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// The instruction.
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let Inst{37} = XT{5};
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let Inst{38-42} = XT{4-0};
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let Inst{43-47} = D_RA{38-34}; // RA
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let Inst{48-63} = D_RA{15-0}; // d1
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}
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multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>,
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isPCRel;
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}
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multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>, isPCRel;
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}
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multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>,
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isPCRel;
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}
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def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
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let Predicates = [PrefixInstrs] in {
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PADDI8 :
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MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
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(ins immZero:$RA, s34imm:$SI),
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"paddi $RT, $RA, $SI", IIC_LdStLFD>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
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(ins s34imm:$SI),
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"pli $RT, $SI", IIC_IntSimple, []>;
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}
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}
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defm PADDI :
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MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
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(ins immZero:$RA, s34imm:$SI),
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"paddi $RT, $RA, $SI", IIC_LdStLFD>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
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(ins s34imm:$SI),
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"pli $RT, $SI", IIC_IntSimple, []>;
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}
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let mayLoad = 1, mayStore = 0 in {
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defm PLXV :
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8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
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IIC_LdStLFD>;
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defm PLFS :
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MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
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IIC_LdStLFD>;
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defm PLFD :
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MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
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IIC_LdStLFD>;
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defm PLXSSP :
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8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
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IIC_LdStLFD>;
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defm PLXSD :
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8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
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IIC_LdStLFD>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PLBZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHA8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWA8 :
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8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
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IIC_LdStLFD>;
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}
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defm PLBZ :
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MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHZ :
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MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHA :
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MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWZ :
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MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWA :
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8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLD :
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8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
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IIC_LdStLFD>;
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}
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let mayStore = 1, mayLoad = 0 in {
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defm PSTXV :
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8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
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(ins vsrc:$XS, memri34_pcrel:$D_RA),
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"pstxv $XS, $D_RA", IIC_LdStLFD>;
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defm PSTFS :
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MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
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(ins f4rc:$FRS, memri34_pcrel:$D_RA),
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"pstfs $FRS, $D_RA", IIC_LdStLFD>;
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defm PSTFD :
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MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
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(ins f8rc:$FRS, memri34_pcrel:$D_RA),
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"pstfd $FRS, $D_RA", IIC_LdStLFD>;
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defm PSTXSSP :
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8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
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(ins vfrc:$VRS, memri34_pcrel:$D_RA),
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"pstxssp $VRS, $D_RA", IIC_LdStLFD>;
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defm PSTXSD :
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8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
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(ins vfrc:$VRS, memri34_pcrel:$D_RA),
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"pstxsd $VRS, $D_RA", IIC_LdStLFD>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PSTB8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"pstb $RS, $D_RA", IIC_LdStLFD>;
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defm PSTH8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"psth $RS, $D_RA", IIC_LdStLFD>;
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defm PSTW8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"pstw $RS, $D_RA", IIC_LdStLFD>;
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}
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defm PSTB :
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MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
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(ins gprc:$RS, memri34_pcrel:$D_RA),
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"pstb $RS, $D_RA", IIC_LdStLFD>;
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defm PSTH :
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MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
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(ins gprc:$RS, memri34_pcrel:$D_RA),
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"psth $RS, $D_RA", IIC_LdStLFD>;
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defm PSTW :
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MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
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(ins gprc:$RS, memri34_pcrel:$D_RA),
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"pstw $RS, $D_RA", IIC_LdStLFD>;
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defm PSTD :
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8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"pstd $RS, $D_RA", IIC_LdStLFD>;
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}
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}
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// TODO: We have an added complexity of 500 here. This is only a temporary
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// solution to have tablegen consider these patterns first. The way we do
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// addressing for PowerPC is complex depending on available D form, X form, or
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// aligned D form loads/stores like DS and DQ forms. The prefixed
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// instructions in this file also add additional PC Relative loads/stores
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// and D form loads/stores with 34 bit immediates. It is very difficult to force
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// instruction selection to consistently pick these first without the current
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// added complexity. Once pc-relative implementation is complete, a set of
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// follow-up patches will address this refactoring and the AddedComplexity will
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// be removed.
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let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
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// Load i32
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def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLBZpc $ga, 0)>;
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def : Pat<(i32 (extloadi8 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLBZpc $ga, 0)>;
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def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLHApc $ga, 0)>;
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def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLHZpc $ga, 0)>;
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def : Pat<(i32 (extloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLHZpc $ga, 0)>;
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def : Pat<(i32 (load (PPCmatpcreladdr pcreladdr:$ga))), (PLWZpc $ga, 0)>;
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// Store i32
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def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTBpc $RS, $ga, 0)>;
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def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTHpc $RS, $ga, 0)>;
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def : Pat<(store i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTWpc $RS, $ga, 0)>;
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// Load i64
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def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLBZ8pc $ga, 0)>;
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def : Pat<(i64 (extloadi8 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLBZ8pc $ga, 0)>;
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def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLHA8pc $ga, 0)>;
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def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLHZ8pc $ga, 0)>;
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def : Pat<(i64 (extloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLHZ8pc $ga, 0)>;
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def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLWZ8pc $ga, 0)>;
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def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLWA8pc $ga, 0)>;
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def : Pat<(i64 (extloadi32 (PPCmatpcreladdr pcreladdr:$ga))),
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(PLWZ8pc $ga, 0)>;
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def : Pat<(i64 (load (PPCmatpcreladdr pcreladdr:$ga))), (PLDpc $ga, 0)>;
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// Store i64
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def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTB8pc $RS, $ga, 0)>;
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def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTH8pc $RS, $ga, 0)>;
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def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTW8pc $RS, $ga, 0)>;
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def : Pat<(store i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTDpc $RS, $ga, 0)>;
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// Load f32
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def : Pat<(f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFSpc $addr, 0)>;
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// Store f32
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def : Pat<(store f32:$FRS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTFSpc $FRS, $ga, 0)>;
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// Load f64
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def : Pat<(f64 (extloadf32 (PPCmatpcreladdr pcreladdr:$addr))),
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(COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
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def : Pat<(f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFDpc $addr, 0)>;
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// Store f64
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def : Pat<(store f64:$FRS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTFDpc $FRS, $ga, 0)>;
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// Load f128
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def : Pat<(f128 (load (PPCmatpcreladdr pcreladdr:$addr))),
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(COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
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// Store f128
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def : Pat<(store f128:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
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// Load v4i32
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def : Pat<(v4i32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Store v4i32
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def : Pat<(store v4i32:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTXVpc $XS, $ga, 0)>;
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// Load v2i64
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def : Pat<(v2i64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Store v2i64
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def : Pat<(store v2i64:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTXVpc $XS, $ga, 0)>;
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// Load v4f32
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def : Pat<(v4f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Store v4f32
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def : Pat<(store v4f32:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTXVpc $XS, $ga, 0)>;
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// Load v2f64
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def : Pat<(v2f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Store v2f64
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def : Pat<(store v2f64:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
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(PSTXVpc $XS, $ga, 0)>;
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// Atomic Load
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def : Pat<(atomic_load_8 (PPCmatpcreladdr pcreladdr:$ga)),
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(PLBZpc $ga, 0)>;
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def : Pat<(atomic_load_16 (PPCmatpcreladdr pcreladdr:$ga)),
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(PLHZpc $ga, 0)>;
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def : Pat<(atomic_load_32 (PPCmatpcreladdr pcreladdr:$ga)),
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(PLWZpc $ga, 0)>;
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def : Pat<(atomic_load_64 (PPCmatpcreladdr pcreladdr:$ga)),
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(PLDpc $ga, 0)>;
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// Atomic Store
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def : Pat<(atomic_store_8 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS),
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(PSTBpc $RS, $ga, 0)>;
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def : Pat<(atomic_store_16 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS),
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(PSTHpc $RS, $ga, 0)>;
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def : Pat<(atomic_store_32 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS),
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(PSTWpc $RS, $ga, 0)>;
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def : Pat<(atomic_store_8 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
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(PSTB8pc $RS, $ga, 0)>;
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def : Pat<(atomic_store_16 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
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(PSTH8pc $RS, $ga, 0)>;
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def : Pat<(atomic_store_32 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
|
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(PSTW8pc $RS, $ga, 0)>;
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def : Pat<(atomic_store_64 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
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(PSTDpc $RS, $ga, 0)>;
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// Special Cases For PPCstore_scal_int_from_vsr
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def : Pat<(PPCstore_scal_int_from_vsr
|
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(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)),
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(PPCmatpcreladdr pcreladdr:$dst), 8),
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(PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>;
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def : Pat<(PPCstore_scal_int_from_vsr
|
|
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)),
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(PPCmatpcreladdr pcreladdr:$dst), 8),
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|
(PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>;
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|
|
|
def : Pat<(PPCstore_scal_int_from_vsr
|
|
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)),
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|
(PPCmatpcreladdr pcreladdr:$dst), 8),
|
|
(PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>;
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|
def : Pat<(PPCstore_scal_int_from_vsr
|
|
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)),
|
|
(PPCmatpcreladdr pcreladdr:$dst), 8),
|
|
(PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
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// If the PPCmatpcreladdr node is not caught by any other pattern it should be
|
|
// caught here and turned into a paddi instruction to materialize the address.
|
|
def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
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}
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