91 lines
3.2 KiB
C++
91 lines
3.2 KiB
C++
//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This file provides AMDGPU specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "AMDGPUMCAsmInfo.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "SIDefines.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "AMDGPUGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AMDGPUGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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static MCInstrInfo *createAMDGPUMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitAMDGPUMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitAMDGPUMCRegisterInfo(X, 0);
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return X;
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}
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static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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MCSubtargetInfo * X = new MCSubtargetInfo();
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InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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X->initMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new AMDGPUInstPrinter(MAI, MII, MRI);
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}
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extern "C" void LLVMInitializeR600TargetMC() {
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for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
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RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
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TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
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TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
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TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
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TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
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TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
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}
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TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
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createR600MCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
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}
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