290 lines
8.2 KiB
C++
290 lines
8.2 KiB
C++
//===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The SI code emitter produces machine code that can be executed
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/// directly on the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
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SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
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void operator=(const SIMCCodeEmitter &) = delete;
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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MCContext &Ctx;
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/// \brief Can this operand also contain immediate values?
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bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
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/// \brief Encode an fp or int literal
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uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const;
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public:
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SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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MCContext &ctx)
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: MCII(mcii), MRI(mri), Ctx(ctx) { }
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~SIMCCodeEmitter() override {}
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/// \brief Encode the instruction and write it to the OS.
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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/// \returns the encoding for an MCOperand.
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uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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/// \brief Use a fixup to encode the simm16 field for SOPP branch
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/// instructions.
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unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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};
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} // End anonymous namespace
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MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new SIMCCodeEmitter(MCII, MRI, Ctx);
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}
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bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
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unsigned OpNo) const {
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unsigned OpType = Desc.OpInfo[OpNo].OperandType;
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return OpType == AMDGPU::OPERAND_REG_IMM32 ||
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OpType == AMDGPU::OPERAND_REG_INLINE_C;
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}
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// Returns the encoding value to use if the given integer is an integer inline
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// immediate value, or 0 if it is not.
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template <typename IntTy>
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static uint32_t getIntInlineImmEncoding(IntTy Imm) {
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if (Imm >= 0 && Imm <= 64)
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return 128 + Imm;
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if (Imm >= -16 && Imm <= -1)
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return 192 + std::abs(Imm);
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return 0;
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}
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static uint32_t getLit32Encoding(uint32_t Val) {
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uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == FloatToBits(0.5f))
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return 240;
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if (Val == FloatToBits(-0.5f))
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return 241;
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if (Val == FloatToBits(1.0f))
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return 242;
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if (Val == FloatToBits(-1.0f))
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return 243;
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if (Val == FloatToBits(2.0f))
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return 244;
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if (Val == FloatToBits(-2.0f))
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return 245;
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if (Val == FloatToBits(4.0f))
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return 246;
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if (Val == FloatToBits(-4.0f))
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return 247;
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return 255;
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}
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static uint32_t getLit64Encoding(uint64_t Val) {
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uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == DoubleToBits(0.5))
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return 240;
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if (Val == DoubleToBits(-0.5))
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return 241;
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if (Val == DoubleToBits(1.0))
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return 242;
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if (Val == DoubleToBits(-1.0))
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return 243;
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if (Val == DoubleToBits(2.0))
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return 244;
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if (Val == DoubleToBits(-2.0))
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return 245;
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if (Val == DoubleToBits(4.0))
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return 246;
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if (Val == DoubleToBits(-4.0))
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return 247;
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return 255;
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}
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uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
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unsigned OpSize) const {
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if (MO.isExpr())
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return 255;
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assert(!MO.isFPImm());
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if (!MO.isImm())
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return ~0;
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if (OpSize == 4)
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return getLit32Encoding(static_cast<uint32_t>(MO.getImm()));
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assert(OpSize == 8);
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return getLit64Encoding(static_cast<uint64_t>(MO.getImm()));
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}
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void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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unsigned bytes = Desc.getSize();
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for (unsigned i = 0; i < bytes; i++) {
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OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
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}
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if (bytes > 4)
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return;
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// Check for additional literals in SRC0/1/2 (Op 1/2/3)
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for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
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// Check if this operand should be encoded as [SV]Src
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if (!isSrcOperand(Desc, i))
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continue;
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int RCID = Desc.OpInfo[i].RegClass;
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const MCRegisterClass &RC = MRI.getRegClass(RCID);
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// Is this operand a literal immediate?
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const MCOperand &Op = MI.getOperand(i);
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if (getLitEncoding(Op, RC.getSize()) != 255)
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continue;
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// Yes! Encode it
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int64_t Imm = 0;
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if (Op.isImm())
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Imm = Op.getImm();
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else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
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llvm_unreachable("Must be immediate or expr");
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for (unsigned j = 0; j < 4; j++) {
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OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
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}
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// Only one literal value allowed
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break;
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}
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}
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unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
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Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
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return 0;
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}
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return getMachineOpValue(MI, MO, Fixups, STI);
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}
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uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return MRI.getEncodingValue(MO.getReg());
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if (MO.isExpr()) {
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const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
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MCFixupKind Kind;
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const MCSymbol *Sym =
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Ctx.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
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if (&Expr->getSymbol() == Sym) {
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// Add the offset to the beginning of the constant values.
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Kind = (MCFixupKind)AMDGPU::fixup_si_end_of_text;
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} else {
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// This is used for constant data stored in .rodata.
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Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
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}
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Fixups.push_back(MCFixup::create(4, Expr, Kind, MI.getLoc()));
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}
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// Figure out the operand number, needed for isSrcOperand check
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unsigned OpNo = 0;
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for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
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if (&MO == &MI.getOperand(OpNo))
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break;
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}
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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if (isSrcOperand(Desc, OpNo)) {
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int RCID = Desc.OpInfo[OpNo].RegClass;
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const MCRegisterClass &RC = MRI.getRegClass(RCID);
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uint32_t Enc = getLitEncoding(MO, RC.getSize());
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if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
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return Enc;
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} else if (MO.isImm())
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return MO.getImm();
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llvm_unreachable("Encoding of this operand type is not supported yet.");
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return 0;
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}
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