1431 lines
37 KiB
TableGen
1431 lines
37 KiB
TableGen
//===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the resources required by P9 instructions. This is part of
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// the P9 processor model used for instruction scheduling. This file should
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// contain all the instructions that may be used on Power 9. This is not
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// just instructions that are new on Power 9 but also instructions that were
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// available on earlier architectures and are still used in Power 9.
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//
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// The makeup of the P9 CPU is modeled as follows:
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// - Each CPU is made up of two superslices.
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// - Each superslice is made up of two slices. Therefore, there are 4 slices
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// for each CPU.
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// - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
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// - Each CPU has:
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// - One CY (Crypto) unit P9_CY_*
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// - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
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// - Two PM (Permute) units. One on each superslice. P9_PM_*
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// - Two DIV (Fixed Point Divide) units. One on each superslize. P9_DIV_*
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// - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
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// - Four DP (Floating Point) units. One on each slice. P9_DP_*
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// This also includes fixed point multiply add.
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// - Four AGEN (Address Generation) units. One for each slice. P9_AGEN_*
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// - Four Load/Store Queues. P9_LS_*
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// - Each set of instructions will require a number of these resources.
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//===----------------------------------------------------------------------===//
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// Two cycle ALU vector operation that uses an entire superslice.
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// Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
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// (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice.
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def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
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(instrs
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(instregex "VADDU(B|H|W|D)M$"),
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(instregex "VAND(C)?$"),
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(instregex "VEXTS(B|H|W)2(D|W)(s)?$"),
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(instregex "V_SET0(B|H)?$"),
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(instregex "VS(R|L)(B|H|W|D)$"),
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(instregex "VSUBU(B|H|W|D)M$"),
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(instregex "VPOPCNT(B|H)$"),
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(instregex "VRL(B|H|W|D)$"),
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(instregex "VSRA(B|H|W|D)$"),
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(instregex "XV(N)?ABS(D|S)P$"),
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(instregex "XVCPSGN(D|S)P$"),
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(instregex "XV(I|X)EXP(D|S)P$"),
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(instregex "VRL(D|W)(MI|NM)$"),
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(instregex "VMRG(E|O)W$"),
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MTVSRDD,
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VEQV,
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VNAND,
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VNEGD,
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VNEGW,
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VNOR,
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VOR,
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VORC,
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VSEL,
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VXOR,
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XVNEGDP,
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XVNEGSP,
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XXLAND,
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XXLANDC,
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XXLEQV,
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XXLEQVOnes,
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XXLNAND,
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XXLNOR,
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XXLOR,
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XXLORf,
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XXLORC,
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XXLXOR,
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XXLXORdpz,
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XXLXORspz,
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XXLXORz,
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XXSEL,
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XSABSQP,
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XSCPSGNQP,
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XSIEXPQP,
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XSNABSQP,
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XSNEGQP,
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XSXEXPQP
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)>;
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// Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
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// single slice. However, since it is Restricted, it requires all 3 dispatches
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// (DISP) for that superslice.
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def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_3SLOTS_1C],
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(instrs
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(instregex "TABORT(D|W)C(I)?$"),
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(instregex "MTFSB(0|1)$"),
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(instregex "MFFSC(D)?RN(I)?$"),
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(instregex "CMPRB(8)?$"),
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(instregex "TD(I)?$"),
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(instregex "TW(I)?$"),
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(instregex "FCMPU(S|D)$"),
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(instregex "XSTSTDC(S|D)P$"),
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FTDIV,
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FTSQRT,
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CMPEQB
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)>;
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// Standard Dispatch ALU operation for 3 cycles. Only one slice used.
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def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C],
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(instrs
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(instregex "XSMAX(C|J)?DP$"),
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(instregex "XSMIN(C|J)?DP$"),
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(instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
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(instregex "CNT(L|T)Z(D|W)(8)?(_rec)?$"),
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(instregex "POPCNT(D|W)$"),
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(instregex "CMPB(8)?$"),
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(instregex "SETB(8)?$"),
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XSTDIVDP,
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XSTSQRTDP,
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XSXSIGDP,
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XSCVSPDPN,
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BPERMD
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)>;
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// Standard Dispatch ALU operation for 2 cycles. Only one slice used.
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def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
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(instrs
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(instregex "S(L|R)D$"),
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(instregex "SRAD(I)?$"),
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(instregex "EXTSWSLI_32_64$"),
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(instregex "MFV(S)?RD$"),
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(instregex "MTV(S)?RD$"),
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(instregex "MTV(S)?RW(A|Z)$"),
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(instregex "CMP(WI|LWI|W|LW)(8)?$"),
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(instregex "CMP(L)?D(I)?$"),
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(instregex "SUBF(I)?C(8)?(O)?$"),
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(instregex "ANDI(S)?(8)?(_rec)?$"),
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(instregex "ADDC(8)?(O)?$"),
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(instregex "ADDIC(8)?(_rec)?$"),
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(instregex "ADD(8|4)(O)?(_rec)?$"),
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(instregex "ADD(E|ME|ZE)(8)?(O)?(_rec)?$"),
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(instregex "SUBF(E|ME|ZE)?(8)?(O)?(_rec)?$"),
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(instregex "NEG(8)?(O)?(_rec)?$"),
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(instregex "POPCNTB$"),
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(instregex "ADD(I|IS)?(8)?$"),
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(instregex "LI(S)?(8)?$"),
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(instregex "(X)?OR(I|IS)?(8)?(_rec)?$"),
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(instregex "NAND(8)?(_rec)?$"),
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(instregex "AND(C)?(8)?(_rec)?$"),
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(instregex "NOR(8)?(_rec)?$"),
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(instregex "OR(C)?(8)?(_rec)?$"),
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(instregex "EQV(8)?(_rec)?$"),
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(instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"),
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(instregex "ADD(4|8)(TLS)?(_)?$"),
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(instregex "NEG(8)?(O)?$"),
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(instregex "ADDI(S)?toc(HA|L)(8)?$"),
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COPY,
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MCRF,
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MCRXRX,
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XSNABSDP,
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XSXEXPDP,
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XSABSDP,
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XSNEGDP,
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XSCPSGNDP,
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MFVSRWZ,
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MFVRWZ,
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EXTSWSLI,
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SRADI_32,
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RLDIC,
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RFEBB,
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LA,
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TBEGIN,
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TRECHKPT,
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NOP,
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WAIT
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)>;
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// Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
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// single slice. However, since it is Restricted, it requires all 3 dispatches
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// (DISP) for that superslice.
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def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_3SLOTS_1C],
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(instrs
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(instregex "RLDC(L|R)$"),
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(instregex "RLWIMI(8)?$"),
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(instregex "RLDIC(L|R)(_32)?(_64)?$"),
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(instregex "M(F|T)OCRF(8)?$"),
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(instregex "CR(6)?(UN)?SET$"),
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(instregex "CR(N)?(OR|AND)(C)?$"),
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(instregex "S(L|R)W(8)?$"),
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(instregex "RLW(INM|NM)(8)?$"),
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(instregex "F(N)?ABS(D|S)$"),
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(instregex "FNEG(D|S)$"),
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(instregex "FCPSGN(D|S)$"),
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(instregex "SRAW(I)?$"),
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(instregex "ISEL(8)?$"),
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RLDIMI,
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XSIEXPDP,
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FMR,
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CREQV,
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CRXOR,
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TRECLAIM,
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TSR,
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TABORT
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)>;
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// Three cycle ALU vector operation that uses an entire superslice.
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// Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
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// (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice.
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def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
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(instrs
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(instregex "M(T|F)VSCR$"),
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(instregex "VCMPNEZ(B|H|W)$"),
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(instregex "VCMPEQU(B|H|W|D)$"),
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(instregex "VCMPNE(B|H|W)$"),
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(instregex "VABSDU(B|H|W)$"),
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(instregex "VADDU(B|H|W)S$"),
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(instregex "VAVG(S|U)(B|H|W)$"),
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(instregex "VCMP(EQ|GE|GT)FP(_rec)?$"),
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(instregex "VCMPBFP(_rec)?$"),
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(instregex "VC(L|T)Z(B|H|W|D)$"),
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(instregex "VADDS(B|H|W)S$"),
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(instregex "V(MIN|MAX)FP$"),
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(instregex "V(MIN|MAX)(S|U)(B|H|W|D)$"),
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VBPERMD,
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VADDCUW,
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VPOPCNTW,
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VPOPCNTD,
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VPRTYBD,
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VPRTYBW,
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VSHASIGMAD,
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VSHASIGMAW,
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VSUBSBS,
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VSUBSHS,
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VSUBSWS,
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VSUBUBS,
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VSUBUHS,
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VSUBUWS,
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VSUBCUW,
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VCMPGTSB,
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VCMPGTSB_rec,
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VCMPGTSD,
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VCMPGTSD_rec,
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VCMPGTSH,
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VCMPGTSH_rec,
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VCMPGTSW,
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VCMPGTSW_rec,
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VCMPGTUB,
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VCMPGTUB_rec,
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VCMPGTUD,
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VCMPGTUD_rec,
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VCMPGTUH,
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VCMPGTUH_rec,
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VCMPGTUW,
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VCMPGTUW_rec,
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VCMPNEB_rec,
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VCMPNEH_rec,
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VCMPNEW_rec,
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VCMPNEZB_rec,
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VCMPNEZH_rec,
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VCMPNEZW_rec,
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VCMPEQUB_rec,
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VCMPEQUD_rec,
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VCMPEQUH_rec,
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VCMPEQUW_rec,
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XVCMPEQDP,
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XVCMPEQDP_rec,
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XVCMPEQSP,
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XVCMPEQSP_rec,
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XVCMPGEDP,
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XVCMPGEDP_rec,
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XVCMPGESP,
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XVCMPGESP_rec,
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XVCMPGTDP,
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XVCMPGTDP_rec,
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XVCMPGTSP,
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XVCMPGTSP_rec,
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XVMAXDP,
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XVMAXSP,
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XVMINDP,
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XVMINSP,
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XVTDIVDP,
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XVTDIVSP,
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XVTSQRTDP,
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XVTSQRTSP,
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XVTSTDCDP,
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XVTSTDCSP,
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XVXSIGDP,
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XVXSIGSP
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)>;
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// 7 cycle DP vector operation that uses an entire superslice.
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// Uses both DP units (the even DPE and odd DPO units), two pipelines (EXECE,
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// EXECO) and all three dispatches (DISP) to the given superslice.
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def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
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(instrs
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VADDFP,
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VCTSXS,
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VCTSXS_0,
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VCTUXS,
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VCTUXS_0,
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VEXPTEFP,
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VLOGEFP,
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VMADDFP,
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VMHADDSHS,
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VNMSUBFP,
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VREFP,
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VRFIM,
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VRFIN,
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VRFIP,
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VRFIZ,
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VRSQRTEFP,
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VSUBFP,
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XVADDDP,
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XVADDSP,
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XVCVDPSP,
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XVCVDPSXDS,
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XVCVDPSXWS,
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XVCVDPUXDS,
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XVCVDPUXWS,
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XVCVHPSP,
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XVCVSPDP,
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XVCVSPHP,
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XVCVSPSXDS,
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XVCVSPSXWS,
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XVCVSPUXDS,
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XVCVSPUXWS,
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XVCVSXDDP,
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XVCVSXDSP,
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XVCVSXWDP,
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XVCVSXWSP,
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XVCVUXDDP,
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XVCVUXDSP,
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XVCVUXWDP,
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XVCVUXWSP,
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XVMADDADP,
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XVMADDASP,
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XVMADDMDP,
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XVMADDMSP,
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XVMSUBADP,
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XVMSUBASP,
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XVMSUBMDP,
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XVMSUBMSP,
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XVMULDP,
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XVMULSP,
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XVNMADDADP,
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XVNMADDASP,
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XVNMADDMDP,
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XVNMADDMSP,
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XVNMSUBADP,
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XVNMSUBASP,
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XVNMSUBMDP,
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XVNMSUBMSP,
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XVRDPI,
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XVRDPIC,
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XVRDPIM,
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XVRDPIP,
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XVRDPIZ,
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XVREDP,
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XVRESP,
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XVRSPI,
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XVRSPIC,
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XVRSPIM,
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XVRSPIP,
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XVRSPIZ,
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XVRSQRTEDP,
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XVRSQRTESP,
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|
XVSUBDP,
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|
XVSUBSP,
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|
VCFSX,
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VCFSX_0,
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VCFUX,
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VCFUX_0,
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|
VMHRADDSHS,
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|
VMLADDUHM,
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|
VMSUMMBM,
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|
VMSUMSHM,
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|
VMSUMSHS,
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|
VMSUMUBM,
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|
VMSUMUHM,
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|
VMSUMUHS,
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VMULESB,
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VMULESH,
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VMULESW,
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VMULEUB,
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|
VMULEUH,
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|
VMULEUW,
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|
VMULOSB,
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|
VMULOSH,
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|
VMULOSW,
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|
VMULOUB,
|
|
VMULOUH,
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|
VMULOUW,
|
|
VMULUWM,
|
|
VSUM2SWS,
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|
VSUM4SBS,
|
|
VSUM4SHS,
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|
VSUM4UBS,
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|
VSUMSWS
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|
)>;
|
|
|
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// 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
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// dispatch units for the superslice.
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def : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_3SLOTS_1C],
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|
(instrs
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(instregex "MADD(HD|HDU|LD|LD8)$"),
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|
(instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?(O)?$")
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|
)>;
|
|
|
|
// 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
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|
// dispatch units for the superslice.
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|
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_3SLOTS_1C],
|
|
(instrs
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FRSP,
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|
(instregex "FRI(N|P|Z|M)(D|S)$"),
|
|
(instregex "FRE(S)?$"),
|
|
(instregex "FADD(S)?$"),
|
|
(instregex "FMSUB(S)?$"),
|
|
(instregex "FMADD(S)?$"),
|
|
(instregex "FSUB(S)?$"),
|
|
(instregex "FCFID(U)?(S)?$"),
|
|
(instregex "FCTID(U)?(Z)?$"),
|
|
(instregex "FCTIW(U)?(Z)?$"),
|
|
(instregex "FRSQRTE(S)?$"),
|
|
FNMADDS,
|
|
FNMADD,
|
|
FNMSUBS,
|
|
FNMSUB,
|
|
FSELD,
|
|
FSELS,
|
|
FMULS,
|
|
FMUL,
|
|
XSMADDADP,
|
|
XSMADDASP,
|
|
XSMADDMDP,
|
|
XSMADDMSP,
|
|
XSMSUBADP,
|
|
XSMSUBASP,
|
|
XSMSUBMDP,
|
|
XSMSUBMSP,
|
|
XSMULDP,
|
|
XSMULSP,
|
|
XSNMADDADP,
|
|
XSNMADDASP,
|
|
XSNMADDMDP,
|
|
XSNMADDMSP,
|
|
XSNMSUBADP,
|
|
XSNMSUBASP,
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|
XSNMSUBMDP,
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|
XSNMSUBMSP
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|
)>;
|
|
|
|
// 7 cycle Restricted DP operation and one 3 cycle ALU operation.
|
|
// These operations can be done in parallel. The DP is restricted so we need a
|
|
// full 4 dispatches.
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|
def : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
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|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
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|
(instregex "FSEL(D|S)_rec$")
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|
)>;
|
|
|
|
// 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
|
|
def : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "MUL(H|L)(D|W)(U)?(O)?_rec$")
|
|
)>;
|
|
|
|
// 7 cycle Restricted DP operation and one 3 cycle ALU operation.
|
|
// These operations must be done sequentially.The DP is restricted so we need a
|
|
// full 4 dispatches.
|
|
def : InstRW<[P9_DPOpAndALU2Op_10C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "FRI(N|P|Z|M)(D|S)_rec$"),
|
|
(instregex "FRE(S)?_rec$"),
|
|
(instregex "FADD(S)?_rec$"),
|
|
(instregex "FSUB(S)?_rec$"),
|
|
(instregex "F(N)?MSUB(S)?_rec$"),
|
|
(instregex "F(N)?MADD(S)?_rec$"),
|
|
(instregex "FCFID(U)?(S)?_rec$"),
|
|
(instregex "FCTID(U)?(Z)?_rec$"),
|
|
(instregex "FCTIW(U)?(Z)?_rec$"),
|
|
(instregex "FMUL(S)?_rec$"),
|
|
(instregex "FRSQRTE(S)?_rec$"),
|
|
FRSP_rec
|
|
)>;
|
|
|
|
// 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units.
|
|
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C],
|
|
(instrs
|
|
XSADDDP,
|
|
XSADDSP,
|
|
XSCVDPHP,
|
|
XSCVDPSP,
|
|
XSCVDPSXDS,
|
|
XSCVDPSXDSs,
|
|
XSCVDPSXWS,
|
|
XSCVDPUXDS,
|
|
XSCVDPUXDSs,
|
|
XSCVDPUXWS,
|
|
XSCVDPSXWSs,
|
|
XSCVDPUXWSs,
|
|
XSCVHPDP,
|
|
XSCVSPDP,
|
|
XSCVSXDDP,
|
|
XSCVSXDSP,
|
|
XSCVUXDDP,
|
|
XSCVUXDSP,
|
|
XSRDPI,
|
|
XSRDPIC,
|
|
XSRDPIM,
|
|
XSRDPIP,
|
|
XSRDPIZ,
|
|
XSREDP,
|
|
XSRESP,
|
|
XSRSQRTEDP,
|
|
XSRSQRTESP,
|
|
XSSUBDP,
|
|
XSSUBSP,
|
|
XSCVDPSPN,
|
|
XSRSP
|
|
)>;
|
|
|
|
// Three Cycle PM operation. Only one PM unit per superslice so we use the whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LVS(L|R)$"),
|
|
(instregex "VSPLTIS(W|H|B)$"),
|
|
(instregex "VSPLT(W|H|B)(s)?$"),
|
|
(instregex "V_SETALLONES(B|H)?$"),
|
|
(instregex "VEXTRACTU(B|H|W)$"),
|
|
(instregex "VINSERT(B|H|W|D)$"),
|
|
MFVSRLD,
|
|
MTVSRWS,
|
|
VBPERMQ,
|
|
VCLZLSBB,
|
|
VCTZLSBB,
|
|
VEXTRACTD,
|
|
VEXTUBLX,
|
|
VEXTUBRX,
|
|
VEXTUHLX,
|
|
VEXTUHRX,
|
|
VEXTUWLX,
|
|
VEXTUWRX,
|
|
VGBBD,
|
|
VMRGHB,
|
|
VMRGHH,
|
|
VMRGHW,
|
|
VMRGLB,
|
|
VMRGLH,
|
|
VMRGLW,
|
|
VPERM,
|
|
VPERMR,
|
|
VPERMXOR,
|
|
VPKPX,
|
|
VPKSDSS,
|
|
VPKSDUS,
|
|
VPKSHSS,
|
|
VPKSHUS,
|
|
VPKSWSS,
|
|
VPKSWUS,
|
|
VPKUDUM,
|
|
VPKUDUS,
|
|
VPKUHUM,
|
|
VPKUHUS,
|
|
VPKUWUM,
|
|
VPKUWUS,
|
|
VPRTYBQ,
|
|
VSL,
|
|
VSLDOI,
|
|
VSLO,
|
|
VSLV,
|
|
VSR,
|
|
VSRO,
|
|
VSRV,
|
|
VUPKHPX,
|
|
VUPKHSB,
|
|
VUPKHSH,
|
|
VUPKHSW,
|
|
VUPKLPX,
|
|
VUPKLSB,
|
|
VUPKLSH,
|
|
VUPKLSW,
|
|
XXBRD,
|
|
XXBRH,
|
|
XXBRQ,
|
|
XXBRW,
|
|
XXEXTRACTUW,
|
|
XXINSERTW,
|
|
XXMRGHW,
|
|
XXMRGLW,
|
|
XXPERM,
|
|
XXPERMR,
|
|
XXSLDWI,
|
|
XXSLDWIs,
|
|
XXSPLTIB,
|
|
XXSPLTW,
|
|
XXSPLTWs,
|
|
XXPERMDI,
|
|
XXPERMDIs,
|
|
VADDCUQ,
|
|
VADDECUQ,
|
|
VADDEUQM,
|
|
VADDUQM,
|
|
VMUL10CUQ,
|
|
VMUL10ECUQ,
|
|
VMUL10EUQ,
|
|
VMUL10UQ,
|
|
VSUBCUQ,
|
|
VSUBECUQ,
|
|
VSUBEUQM,
|
|
VSUBUQM,
|
|
XSCMPEXPQP,
|
|
XSCMPOQP,
|
|
XSCMPUQP,
|
|
XSTSTDCQP,
|
|
XSXSIGQP,
|
|
BCDCFN_rec,
|
|
BCDCFZ_rec,
|
|
BCDCPSGN_rec,
|
|
BCDCTN_rec,
|
|
BCDCTZ_rec,
|
|
BCDSETSGN_rec,
|
|
BCDS_rec,
|
|
BCDTRUNC_rec,
|
|
BCDUS_rec,
|
|
BCDUTRUNC_rec
|
|
)>;
|
|
|
|
// 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
|
|
(instrs
|
|
BCDSR_rec,
|
|
XSADDQP,
|
|
XSADDQPO,
|
|
XSCVDPQP,
|
|
XSCVQPDP,
|
|
XSCVQPDPO,
|
|
XSCVQPSDZ,
|
|
XSCVQPSWZ,
|
|
XSCVQPUDZ,
|
|
XSCVQPUWZ,
|
|
XSCVSDQP,
|
|
XSCVUDQP,
|
|
XSRQPI,
|
|
XSRQPIX,
|
|
XSRQPXP,
|
|
XSSUBQP,
|
|
XSSUBQPO
|
|
)>;
|
|
|
|
// 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_DFU_23C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
|
|
(instrs
|
|
BCDCTSQ_rec
|
|
)>;
|
|
|
|
// 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
|
|
(instrs
|
|
XSMADDQP,
|
|
XSMADDQPO,
|
|
XSMSUBQP,
|
|
XSMSUBQPO,
|
|
XSMULQP,
|
|
XSMULQPO,
|
|
XSNMADDQP,
|
|
XSNMADDQPO,
|
|
XSNMSUBQP,
|
|
XSNMSUBQPO
|
|
)>;
|
|
|
|
// 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_DFU_37C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
|
|
(instrs
|
|
BCDCFSQ_rec
|
|
)>;
|
|
|
|
// 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
|
|
(instrs
|
|
XSDIVQP,
|
|
XSDIVQPO
|
|
)>;
|
|
|
|
// 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
|
// dispatches.
|
|
def : InstRW<[P9_DFU_76C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
|
|
(instrs
|
|
XSSQRTQP,
|
|
XSSQRTQPO
|
|
)>;
|
|
|
|
// 6 Cycle Load uses a single slice.
|
|
def : InstRW<[P9_LS_6C, IP_AGEN_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LXVL(L)?")
|
|
)>;
|
|
|
|
// 5 Cycle Load uses a single slice.
|
|
def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LVE(B|H|W)X$"),
|
|
(instregex "LVX(L)?"),
|
|
(instregex "LXSI(B|H)ZX$"),
|
|
LXSDX,
|
|
LXVB16X,
|
|
LXVD2X,
|
|
LXVWSX,
|
|
LXSIWZX,
|
|
LXV,
|
|
LXVX,
|
|
LXSD,
|
|
DFLOADf64,
|
|
XFLOADf64,
|
|
LIWZX
|
|
)>;
|
|
|
|
// 4 Cycle Load uses a single slice.
|
|
def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "DCB(F|T|ST)(EP)?$"),
|
|
(instregex "DCBZ(L)?(EP)?$"),
|
|
(instregex "DCBTST(EP)?$"),
|
|
(instregex "CP_COPY(8)?$"),
|
|
(instregex "CP_PASTE(8)?$"),
|
|
(instregex "ICBI(EP)?$"),
|
|
(instregex "ICBT(LS)?$"),
|
|
(instregex "LBARX(L)?$"),
|
|
(instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"),
|
|
(instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"),
|
|
(instregex "LH(A|B)RX(L)?(8)?$"),
|
|
(instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
|
|
(instregex "LWARX(L)?$"),
|
|
(instregex "LWBRX(8)?$"),
|
|
(instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
|
|
CP_ABORT,
|
|
DARN,
|
|
EnforceIEIO,
|
|
ISYNC,
|
|
MSGSYNC,
|
|
TLBSYNC,
|
|
SYNC,
|
|
LMW,
|
|
LSWI
|
|
)>;
|
|
|
|
// 4 Cycle Restricted load uses a single slice but the dispatch for the whole
|
|
// superslice.
|
|
def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
LFIWZX,
|
|
LFDX,
|
|
LFD
|
|
)>;
|
|
|
|
// Cracked Load Instructions.
|
|
// Load instructions that can be done in parallel.
|
|
def : InstRW<[P9_LS_4C, P9_LS_4C, IP_AGEN_1C, IP_AGEN_1C,
|
|
DISP_PAIR_1C],
|
|
(instrs
|
|
SLBIA,
|
|
SLBIE,
|
|
SLBMFEE,
|
|
SLBMFEV,
|
|
SLBMTE,
|
|
TLBIEL
|
|
)>;
|
|
|
|
// Cracked Load Instruction.
|
|
// Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
|
|
// operations can be run in parallel.
|
|
def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_AGEN_1C,
|
|
DISP_PAIR_1C, DISP_PAIR_1C],
|
|
(instrs
|
|
(instregex "L(W|H)ZU(X)?(8)?$")
|
|
)>;
|
|
|
|
// Cracked TEND Instruction.
|
|
// Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
|
|
// operations can be run in parallel.
|
|
def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_AGEN_1C,
|
|
DISP_1C, DISP_1C],
|
|
(instrs
|
|
TEND
|
|
)>;
|
|
|
|
|
|
// Cracked Store Instruction
|
|
// Consecutive Store and ALU instructions. The store is restricted and requires
|
|
// three dispatches.
|
|
def : InstRW<[P9_StoreAndALUOp_3C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "ST(B|H|W|D)CX$")
|
|
)>;
|
|
|
|
// Cracked Load Instruction.
|
|
// Two consecutive load operations for a total of 8 cycles.
|
|
def : InstRW<[P9_LoadAndLoadOp_8C, IP_AGEN_1C, IP_AGEN_1C,
|
|
DISP_1C, DISP_1C],
|
|
(instrs
|
|
LDMX
|
|
)>;
|
|
|
|
// Cracked Load instruction.
|
|
// Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
|
|
// operations cannot be done at the same time and so their latencies are added.
|
|
def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
|
|
DISP_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LHA(X)?(8)?$"),
|
|
(instregex "CP_PASTE(8)?_rec$"),
|
|
(instregex "LWA(X)?(_32)?$"),
|
|
TCHECK
|
|
)>;
|
|
|
|
// Cracked Restricted Load instruction.
|
|
// Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
|
|
// operations cannot be done at the same time and so their latencies are added.
|
|
// Full 6 dispatches are required as this is both cracked and restricted.
|
|
def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
LFIWAX
|
|
)>;
|
|
|
|
// Cracked Load instruction.
|
|
// Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
|
|
// operations cannot be done at the same time and so their latencies are added.
|
|
// Full 4 dispatches are required as this is a cracked instruction.
|
|
def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
|
(instrs
|
|
LXSIWAX,
|
|
LIWAX
|
|
)>;
|
|
|
|
// Cracked Load instruction.
|
|
// Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7
|
|
// cycles. The Load and ALU operations cannot be done at the same time and so
|
|
// their latencies are added.
|
|
// Full 6 dispatches are required as this is a restricted instruction.
|
|
def : InstRW<[P9_LoadAndALU2Op_7C, IP_AGEN_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
LFSX,
|
|
LFS
|
|
)>;
|
|
|
|
// Cracked Load instruction.
|
|
// Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
|
|
// operations cannot be done at the same time and so their latencies are added.
|
|
// Full 4 dispatches are required as this is a cracked instruction.
|
|
def : InstRW<[P9_LoadAndALU2Op_8C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
|
(instrs
|
|
LXSSP,
|
|
LXSSPX,
|
|
XFLOADf32,
|
|
DFLOADf32
|
|
)>;
|
|
|
|
// Cracked 3-Way Load Instruction
|
|
// Load with two ALU operations that depend on each other
|
|
def : InstRW<[P9_LoadAndALUOp_6C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_PAIR_1C, DISP_PAIR_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LHAU(X)?(8)?$"),
|
|
LWAUX
|
|
)>;
|
|
|
|
// Cracked Load that requires the PM resource.
|
|
// Since the Load and the PM cannot be done at the same time the latencies are
|
|
// added. Requires 8 cycles. Since the PM requires the full superslice we need
|
|
// both EXECE, EXECO pipelines as well as 1 dispatch for the PM. The Load
|
|
// requires the remaining 1 dispatch.
|
|
def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C,
|
|
DISP_1C, DISP_1C],
|
|
(instrs
|
|
LXVH8X,
|
|
LXVDSX,
|
|
LXVW4X
|
|
)>;
|
|
|
|
// Single slice Restricted store operation. The restricted operation requires
|
|
// all three dispatches for the superslice.
|
|
def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
(instregex "STF(S|D|IWX|SX|DX)$"),
|
|
(instregex "STXS(D|DX|SPX|IWX|IBX|IHX|SP)(v)?$"),
|
|
(instregex "STW(8)?$"),
|
|
(instregex "(D|X)FSTORE(f32|f64)$"),
|
|
(instregex "ST(W|H|D)BRX$"),
|
|
(instregex "ST(B|H|D)(8)?$"),
|
|
(instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?(_)?$"),
|
|
STIWX,
|
|
SLBIEG,
|
|
STMW,
|
|
STSWI,
|
|
TLBIE
|
|
)>;
|
|
|
|
// Vector Store Instruction
|
|
// Requires the whole superslice and therefore requires one dispatch
|
|
// as well as both the Even and Odd exec pipelines.
|
|
def : InstRW<[P9_LS_1C, IP_EXECE_1C, IP_EXECO_1C, IP_AGEN_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "STVE(B|H|W)X$"),
|
|
(instregex "STVX(L)?$"),
|
|
(instregex "STXV(B16X|H8X|W4X|D2X|L|LL|X)?$")
|
|
)>;
|
|
|
|
// 5 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and two
|
|
// dispatches.
|
|
def : InstRW<[P9_DIV_5C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
|
|
(instrs
|
|
(instregex "MTCTR(8)?(loop)?$"),
|
|
(instregex "MTLR(8)?$")
|
|
)>;
|
|
|
|
// 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and two
|
|
// dispatches.
|
|
def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
|
|
(instrs
|
|
(instregex "M(T|F)VRSAVE(v)?$"),
|
|
(instregex "M(T|F)PMR$"),
|
|
(instregex "M(T|F)TB(8)?$"),
|
|
(instregex "MF(SPR|CTR|LR)(8)?$"),
|
|
(instregex "M(T|F)MSR(D)?$"),
|
|
(instregex "MTSPR(8)?$")
|
|
)>;
|
|
|
|
// 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and two
|
|
// dispatches.
|
|
def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
|
|
(instrs
|
|
DIVW,
|
|
DIVWO,
|
|
DIVWU,
|
|
DIVWUO,
|
|
MODSW
|
|
)>;
|
|
|
|
// 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and two
|
|
// dispatches.
|
|
def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
|
|
(instrs
|
|
DIVWE,
|
|
DIVWEO,
|
|
DIVD,
|
|
DIVDO,
|
|
DIVWEU,
|
|
DIVWEUO,
|
|
DIVDU,
|
|
DIVDUO,
|
|
MODSD,
|
|
MODUD,
|
|
MODUW
|
|
)>;
|
|
|
|
// 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
|
// dispatches.
|
|
def : InstRW<[P9_DIV_40C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
|
|
(instrs
|
|
DIVDE,
|
|
DIVDEO,
|
|
DIVDEU,
|
|
DIVDEUO
|
|
)>;
|
|
|
|
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
|
|
// and one full superslice for the DIV operation since there is only one DIV per
|
|
// superslice. Latency of DIV plus ALU is 26.
|
|
def : InstRW<[P9_IntDivAndALUOp_18C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
|
|
DISP_EVEN_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "DIVW(U)?(O)?_rec$")
|
|
)>;
|
|
|
|
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
|
|
// and one full superslice for the DIV operation since there is only one DIV per
|
|
// superslice. Latency of DIV plus ALU is 26.
|
|
def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
|
|
DISP_EVEN_1C, DISP_1C],
|
|
(instrs
|
|
DIVD_rec,
|
|
DIVDO_rec,
|
|
DIVDU_rec,
|
|
DIVDUO_rec,
|
|
DIVWE_rec,
|
|
DIVWEO_rec,
|
|
DIVWEU_rec,
|
|
DIVWEUO_rec
|
|
)>;
|
|
|
|
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
|
|
// and one full superslice for the DIV operation since there is only one DIV per
|
|
// superslice. Latency of DIV plus ALU is 42.
|
|
def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
|
|
DISP_EVEN_1C, DISP_1C],
|
|
(instrs
|
|
DIVDE_rec,
|
|
DIVDEO_rec,
|
|
DIVDEU_rec,
|
|
DIVDEUO_rec
|
|
)>;
|
|
|
|
// CR access instructions in _BrMCR, IIC_BrMCRX.
|
|
|
|
// Cracked, restricted, ALU operations.
|
|
// Here the two ALU ops can actually be done in parallel and therefore the
|
|
// latencies are not added together. Otherwise this is like having two
|
|
// instructions running together on two pipelines and 6 dispatches. ALU ops are
|
|
// 2 cycles each.
|
|
def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
MTCRF,
|
|
MTCRF8
|
|
)>;
|
|
|
|
// Cracked ALU operations.
|
|
// Here the two ALU ops can actually be done in parallel and therefore the
|
|
// latencies are not added together. Otherwise this is like having two
|
|
// instructions running together on two pipelines and 2 dispatches. ALU ops are
|
|
// 2 cycles each.
|
|
def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "ADDC(8)?(O)?_rec$"),
|
|
(instregex "SUBFC(8)?(O)?_rec$")
|
|
)>;
|
|
|
|
// Cracked ALU operations.
|
|
// Two ALU ops can be done in parallel.
|
|
// One is three cycle ALU the ohter is a two cycle ALU.
|
|
// One of the ALU ops is restricted the other is not so we have a total of
|
|
// 5 dispatches.
|
|
def : InstRW<[P9_ALU_2C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "F(N)?ABS(D|S)_rec$"),
|
|
(instregex "FCPSGN(D|S)_rec$"),
|
|
(instregex "FNEG(D|S)_rec$"),
|
|
FMR_rec
|
|
)>;
|
|
|
|
// Cracked ALU operations.
|
|
// Here the two ALU ops can actually be done in parallel and therefore the
|
|
// latencies are not added together. Otherwise this is like having two
|
|
// instructions running together on two pipelines and 2 dispatches.
|
|
// ALU ops are 3 cycles each.
|
|
def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_1C, DISP_1C],
|
|
(instrs
|
|
MCRFS
|
|
)>;
|
|
|
|
// Cracked Restricted ALU operations.
|
|
// Here the two ALU ops can actually be done in parallel and therefore the
|
|
// latencies are not added together. Otherwise this is like having two
|
|
// instructions running together on two pipelines and 6 dispatches.
|
|
// ALU ops are 3 cycles each.
|
|
def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
(instregex "MTFSF(b|_rec)?$"),
|
|
(instregex "MTFSFI(_rec)?$")
|
|
)>;
|
|
|
|
// Cracked instruction made of two ALU ops.
|
|
// The two ops cannot be done in parallel.
|
|
// One of the ALU ops is restricted and takes 3 dispatches.
|
|
def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "RLD(I)?C(R|L)_rec$"),
|
|
(instregex "RLW(IMI|INM|NM)(8)?_rec$"),
|
|
(instregex "SLW(8)?_rec$"),
|
|
(instregex "SRAW(I)?_rec$"),
|
|
(instregex "SRW(8)?_rec$"),
|
|
RLDICL_32_rec,
|
|
RLDIMI_rec
|
|
)>;
|
|
|
|
// Cracked instruction made of two ALU ops.
|
|
// The two ops cannot be done in parallel.
|
|
// Both of the ALU ops are restricted and take 3 dispatches.
|
|
def : InstRW<[P9_ALU2OpAndALU2Op_6C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
(instregex "MFFS(L|CE|_rec)?$")
|
|
)>;
|
|
|
|
// Cracked ALU instruction composed of three consecutive 2 cycle loads for a
|
|
// total of 6 cycles. All of the ALU operations are also restricted so each
|
|
// takes 3 dispatches for a total of 9.
|
|
def : InstRW<[P9_ALUOpAndALUOpAndALUOp_6C, IP_EXEC_1C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
(instregex "MFCR(8)?$")
|
|
)>;
|
|
|
|
// Cracked instruction made of two ALU ops.
|
|
// The two ops cannot be done in parallel.
|
|
def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "EXTSWSLI_32_64_rec$"),
|
|
(instregex "SRAD(I)?_rec$"),
|
|
EXTSWSLI_rec,
|
|
SLD_rec,
|
|
SRD_rec,
|
|
RLDIC_rec
|
|
)>;
|
|
|
|
// 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
|
|
def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
FDIV
|
|
)>;
|
|
|
|
// 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
|
|
def : InstRW<[P9_DPOpAndALU2Op_36C_8, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
FDIV_rec
|
|
)>;
|
|
|
|
// 36 Cycle DP Instruction.
|
|
// Instruction can be done on a single slice.
|
|
def : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_1C],
|
|
(instrs
|
|
XSSQRTDP
|
|
)>;
|
|
|
|
// 36 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
|
|
def : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
FSQRT
|
|
)>;
|
|
|
|
// 36 Cycle DP Vector Instruction.
|
|
def : InstRW<[P9_DPE_36C_10, P9_DPO_36C_10, IP_EXECE_1C, IP_EXECO_1C,
|
|
DISP_1C],
|
|
(instrs
|
|
XVSQRTDP
|
|
)>;
|
|
|
|
// 27 Cycle DP Vector Instruction.
|
|
def : InstRW<[P9_DPE_27C_10, P9_DPO_27C_10, IP_EXECE_1C, IP_EXECO_1C,
|
|
DISP_1C],
|
|
(instrs
|
|
XVSQRTSP
|
|
)>;
|
|
|
|
// 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
|
|
def : InstRW<[P9_DPOpAndALU2Op_39C_10, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
FSQRT_rec
|
|
)>;
|
|
|
|
// 26 Cycle DP Instruction.
|
|
def : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_1C],
|
|
(instrs
|
|
XSSQRTSP
|
|
)>;
|
|
|
|
// 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
|
|
def : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
FSQRTS
|
|
)>;
|
|
|
|
// 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
|
|
def : InstRW<[P9_DPOpAndALU2Op_29C_5, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
FSQRTS_rec
|
|
)>;
|
|
|
|
// 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
|
|
def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C],
|
|
(instrs
|
|
XSDIVDP
|
|
)>;
|
|
|
|
// 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
|
|
def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_3SLOTS_1C],
|
|
(instrs
|
|
FDIVS
|
|
)>;
|
|
|
|
// 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
|
|
def : InstRW<[P9_DPOpAndALU2Op_25C_5, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
FDIVS_rec
|
|
)>;
|
|
|
|
// 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
|
|
def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C],
|
|
(instrs
|
|
XSDIVSP
|
|
)>;
|
|
|
|
// 24 Cycle DP Vector Instruction. Takes one full superslice.
|
|
// Includes both EXECE, EXECO pipelines and 1 dispatch for the given
|
|
// superslice.
|
|
def : InstRW<[P9_DPE_24C_8, P9_DPO_24C_8, IP_EXECE_1C, IP_EXECO_1C,
|
|
DISP_1C],
|
|
(instrs
|
|
XVDIVSP
|
|
)>;
|
|
|
|
// 33 Cycle DP Vector Instruction. Takes one full superslice.
|
|
// Includes both EXECE, EXECO pipelines and 1 dispatch for the given
|
|
// superslice.
|
|
def : InstRW<[P9_DPE_33C_8, P9_DPO_33C_8, IP_EXECE_1C, IP_EXECO_1C,
|
|
DISP_1C],
|
|
(instrs
|
|
XVDIVDP
|
|
)>;
|
|
|
|
// Instruction cracked into three pieces. One Load and two ALU operations.
|
|
// The Load and one of the ALU ops cannot be run at the same time and so the
|
|
// latencies are added together for 6 cycles. The remainaing ALU is 2 cycles.
|
|
// Both the load and the ALU that depends on it are restricted and so they take
|
|
// a total of 7 dispatches. The final 2 dispatches come from the second ALU op.
|
|
// The two EXEC pipelines are for the 2 ALUs while the AGEN is for the load.
|
|
def : InstRW<[P9_LoadAndALU2Op_7C, P9_ALU_2C,
|
|
IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LF(SU|SUX)$")
|
|
)>;
|
|
|
|
// Cracked instruction made up of a Store and an ALU. The ALU does not depend on
|
|
// the store and so it can be run at the same time as the store. The store is
|
|
// also restricted.
|
|
def : InstRW<[P9_LS_1C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "STF(S|D)U(X)?$"),
|
|
(instregex "ST(B|H|W|D)U(X)?(8)?$")
|
|
)>;
|
|
|
|
// Cracked instruction made up of a Load and an ALU. The ALU does not depend on
|
|
// the load and so it can be run at the same time as the load.
|
|
def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
|
|
DISP_PAIR_1C, DISP_PAIR_1C],
|
|
(instrs
|
|
(instregex "LBZU(X)?(8)?$"),
|
|
(instregex "LDU(X)?$")
|
|
)>;
|
|
|
|
// Cracked instruction made up of a Load and an ALU. The ALU does not depend on
|
|
// the load and so it can be run at the same time as the load. The load is also
|
|
// restricted. 3 dispatches are from the restricted load while the other two
|
|
// are from the ALU. The AGEN pipeline is from the load and the EXEC pipeline
|
|
// is required for the ALU.
|
|
def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
|
|
DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "LF(DU|DUX)$")
|
|
)>;
|
|
|
|
// Crypto Instructions
|
|
|
|
// 6 Cycle CY operation. Only one CY unit per CPU so we use a whole
|
|
// superslice. That includes both exec pipelines (EXECO, EXECE) and one
|
|
// dispatch.
|
|
def : InstRW<[P9_CY_6C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "VPMSUM(B|H|W|D)$"),
|
|
(instregex "V(N)?CIPHER(LAST)?$"),
|
|
VSBOX
|
|
)>;
|
|
|
|
// Branch Instructions
|
|
|
|
// Two Cycle Branch
|
|
def : InstRW<[P9_BR_2C, DISP_BR_1C],
|
|
(instrs
|
|
(instregex "BCCCTR(L)?(8)?$"),
|
|
(instregex "BCCL(A|R|RL)?$"),
|
|
(instregex "BCCTR(L)?(8)?(n)?$"),
|
|
(instregex "BD(N)?Z(8|A|Am|Ap|m|p)?$"),
|
|
(instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"),
|
|
(instregex "BL(_TLS|_NOP)?$"),
|
|
(instregex "BL8(_TLS|_NOP|_NOP_TLS|_TLS_)?$"),
|
|
(instregex "BLA(8|8_NOP)?$"),
|
|
(instregex "BLR(8|L)?$"),
|
|
(instregex "TAILB(A)?(8)?$"),
|
|
(instregex "TAILBCTR(8)?$"),
|
|
(instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),
|
|
(instregex "BCLR(L)?(n)?$"),
|
|
(instregex "BCTR(L)?(8)?$"),
|
|
B,
|
|
BA,
|
|
BC,
|
|
BCC,
|
|
BCCA,
|
|
BCL,
|
|
BCLalways,
|
|
BCLn,
|
|
BCTRL8_LDinto_toc,
|
|
BCTRL_LWZinto_toc,
|
|
BCn,
|
|
CTRL_DEP
|
|
)>;
|
|
|
|
// Five Cycle Branch with a 2 Cycle ALU Op
|
|
// Operations must be done consecutively and not in parallel.
|
|
def : InstRW<[P9_BROpAndALUOp_7C, IP_EXEC_1C, DISP_BR_1C, DISP_1C],
|
|
(instrs
|
|
ADDPCIS
|
|
)>;
|
|
|
|
// Special Extracted Instructions For Atomics
|
|
|
|
// Atomic Load
|
|
def : InstRW<[P9_LS_1C, P9_LS_1C, P9_LS_4C, P9_LS_4C, P9_LS_4C,
|
|
IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C, IP_AGEN_1C, IP_AGEN_1C,
|
|
IP_AGEN_1C, IP_AGEN_1C, DISP_1C, DISP_3SLOTS_1C,
|
|
DISP_3SLOTS_1C, DISP_1C, DISP_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "L(D|W)AT$")
|
|
)>;
|
|
|
|
// Atomic Store
|
|
def : InstRW<[P9_LS_1C, P9_LS_4C, P9_LS_4C, IP_EXEC_1C, IP_AGEN_1C, IP_AGEN_1C,
|
|
IP_AGEN_1C, DISP_1C, DISP_3SLOTS_1C, DISP_1C],
|
|
(instrs
|
|
(instregex "ST(D|W)AT$")
|
|
)>;
|
|
|
|
// Signal Processing Engine (SPE) Instructions
|
|
// These instructions are not supported on Power 9
|
|
def : InstRW<[],
|
|
(instrs
|
|
BRINC,
|
|
EVABS,
|
|
EVEQV,
|
|
EVMRA,
|
|
EVNAND,
|
|
EVNEG,
|
|
(instregex "EVADD(I)?W$"),
|
|
(instregex "EVADD(SM|SS|UM|US)IAAW$"),
|
|
(instregex "EVAND(C)?$"),
|
|
(instregex "EVCMP(EQ|GTS|GTU|LTS|LTU)$"),
|
|
(instregex "EVCNTL(S|Z)W$"),
|
|
(instregex "EVDIVW(S|U)$"),
|
|
(instregex "EVEXTS(B|H)$"),
|
|
(instregex "EVLD(H|W|D)(X)?$"),
|
|
(instregex "EVLHH(E|OS|OU)SPLAT(X)?$"),
|
|
(instregex "EVLWHE(X)?$"),
|
|
(instregex "EVLWHO(S|U)(X)?$"),
|
|
(instregex "EVLW(H|W)SPLAT(X)?$"),
|
|
(instregex "EVMERGE(HI|LO|HILO|LOHI)$"),
|
|
(instregex "EVMHEG(S|U)M(F|I)A(A|N)$"),
|
|
(instregex "EVMHES(M|S)(F|I)(A|AA|AAW|ANW)?$"),
|
|
(instregex "EVMHEU(M|S)I(A|AA|AAW|ANW)?$"),
|
|
(instregex "EVMHOG(U|S)M(F|I)A(A|N)$"),
|
|
(instregex "EVMHOS(M|S)(F|I)(A|AA|AAW|ANW)?$"),
|
|
(instregex "EVMHOU(M|S)I(A|AA|ANW|AAW)?$"),
|
|
(instregex "EVMWHS(M|S)(F|FA|I|IA)$"),
|
|
(instregex "EVMWHUMI(A)?$"),
|
|
(instregex "EVMWLS(M|S)IA(A|N)W$"),
|
|
(instregex "EVMWLU(M|S)I(A|AA|AAW|ANW)?$"),
|
|
(instregex "EVMWSM(F|I)(A|AA|AN)?$"),
|
|
(instregex "EVMWSSF(A|AA|AN)?$"),
|
|
(instregex "EVMWUMI(A|AA|AN)?$"),
|
|
(instregex "EV(N|X)?OR(C)?$"),
|
|
(instregex "EVR(LW|LWI|NDW)$"),
|
|
(instregex "EVSLW(I)?$"),
|
|
(instregex "EVSPLAT(F)?I$"),
|
|
(instregex "EVSRW(I)?(S|U)$"),
|
|
(instregex "EVST(DD|DH|DW|WHE|WHO|WWE|WWO)(X)?$"),
|
|
(instregex "EVSUBF(S|U)(M|S)IAAW$"),
|
|
(instregex "EVSUB(I)?FW$")
|
|
)> { let Unsupported = 1; }
|
|
|
|
// General Instructions without scheduling support.
|
|
def : InstRW<[],
|
|
(instrs
|
|
(instregex "(H)?RFI(D)?$"),
|
|
(instregex "DSS(ALL)?$"),
|
|
(instregex "DST(ST)?(T)?(64)?$"),
|
|
(instregex "ICBL(C|Q)$"),
|
|
(instregex "L(W|H|B)EPX$"),
|
|
(instregex "ST(W|H|B)EPX$"),
|
|
(instregex "(L|ST)FDEPX$"),
|
|
(instregex "M(T|F)SR(IN)?$"),
|
|
(instregex "M(T|F)DCR$"),
|
|
(instregex "NOP_GT_PWR(6|7)$"),
|
|
(instregex "TLB(IA|IVAX|SX|SX2|SX2D|LD|LI|RE|RE2|WE|WE2)$"),
|
|
(instregex "WRTEE(I)?$"),
|
|
ATTN,
|
|
CLRBHRB,
|
|
MFBHRBE,
|
|
MBAR,
|
|
MSYNC,
|
|
SLBSYNC,
|
|
SLBFEE_rec,
|
|
NAP,
|
|
STOP,
|
|
TRAP,
|
|
RFCI,
|
|
RFDI,
|
|
RFMCI,
|
|
SC,
|
|
DCBA,
|
|
DCBI,
|
|
DCCCI,
|
|
ICCCI
|
|
)> { let Unsupported = 1; }
|