OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
llvm-project/llvm/lib/Target/RISCV
History
Simon Cook ca950a6bb1 [RISCV] Compress instructions based on function features 
When running under LTO, it is common to not specify the architecture
spec, which is used for setting up the target machine, and instead rely
on features specified in each function to generate the correct
instructions.

This works for the code generator, but the RISC-V backend uses the
AsmPrinter to do instruction compression, which does not see these
features but instead uses a MCSubtargetInfo object to see whether
compression is enabled. Since this is configured based on the
TargetMachine at startup, it will result in compressed instructions not
being emitted when it has not been given the 'c' TargetFeature, but the
function has it.

This changes the RISCVAsmPrinter to re-initialize the STI feature set
based on the current MachineFunction, such that compressed instructions
are now correctly emitted regardless of the method used to enable them.

Differential revision: https://reviews.llvm.org/D73339
 		2020-02-28 11:52:55 +00:00
..
AsmParser [MC] De-capitalize another set of MCStreamer::Emit* functions 2020-02-14 19:26:52 -08:00
Disassembler CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
MCTargetDesc [NFC][RISCV] Fixing typo in comment. 2020-02-05 11:30:11 -08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Utils [RISCV] Support ABI checking with per function target-features 2020-01-22 08:12:28 -08:00
CMakeLists.txt [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
LLVMBuild.txt [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCV.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCV.td [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVAsmPrinter.cpp [RISCV] Compress instructions based on function features 2020-02-28 11:52:55 +00:00
RISCVCallLowering.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVCallLowering.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVCallingConv.td [RISCV] Rename FPRs and use Register arithmetic 2019-09-27 15:49:10 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Use addi rather than add x0 2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVFrameLowering.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVISelDAGToDAG.cpp [SelectionDAG] Disallow indirect "i" constraint 2019-12-29 16:50:42 -08:00
RISCVISelLowering.cpp [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization 2020-02-18 23:56:42 +08:00
RISCVISelLowering.h [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization 2020-02-18 23:56:42 +08:00
RISCVInstrFormats.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td
…
RISCVInstrInfo.cpp [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
RISCVInstrInfo.h [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
RISCVInstrInfo.td [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
RISCVInstrInfoA.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrInfoC.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrInfoF.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrInfoM.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVMergeBaseOffset.cpp [RISCV] Convert registers from unsigned to Register 2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler 2020-02-15 09:14:04 +08:00
RISCVRegisterInfo.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVRegisterInfo.td [RISCV] Rename FPRs and use Register arithmetic 2019-09-27 15:49:10 +00:00
RISCVSchedRocket32.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVSchedRocket64.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVSchedule.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVSubtarget.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
RISCVSubtarget.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVSystemOperands.td [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references 2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp [RISCV] Check the target-abi module flag matches the option 2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h [RISCV] Add subtargets initialized with target feature 2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp Revert "Honor -fuse-init-array when os is not specified on x86" 2019-12-17 07:36:59 -08:00
RISCVTargetObjectFile.h [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00