llvm-project/llvm/test/CodeGen
David Green 1de1070559 [DAGCombine] Fix alias analysis for unaligned accesses
The alias analysis in DAG Combine looks at the BaseAlign, the Offset and
the Size of two accesses, and determines if they are known to access
different parts of memory by the fact that they are different offsets
from inside that "alignment window". It does not seem to account for
accesses that are not a multiple of the size, and may overflow from one
alignment window into another.

For example in the test case we have a 19byte memset that is splits into
a 16 byte neon store and an unaligned 4 byte store with a 15 byte
offset. This 15byte offset (with a base align of 8) wraps around to the
next alignment windows. When compared to an access that is a 16byte
offset (of the same 4byte size and 8byte basealign), the two accesses
are said not to alias.

I've fixed this here by just ensuring that the offsets are a multiple of
the size, ensuring that they don't overlap by wrapping. Fixes PR45035,
which was exposed by the UseAA changes in the arm backend.

Differential Revision: https://reviews.llvm.org/D75238
2020-02-28 18:44:36 +00:00
..
AArch64 No longer generate calls to *_finite 2020-02-28 10:07:37 +01:00
AMDGPU [AMDGPU] Precommit some scheduler related test updates 2020-02-28 11:20:58 +00:00
ARC
ARM [DAGCombine] Fix alias analysis for unaligned accesses 2020-02-28 18:44:36 +00:00
AVR [AVR] Fix private label prefix 2020-02-26 20:32:25 +01:00
BPF Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
Generic Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
Hexagon Reland 7691790dfd with a MSAN fix 2020-02-28 08:32:58 -06:00
Inputs
Lanai Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
MIR Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
MSP430
Mips [MIPS GlobalISel] Legalize non-power-of-2 and unaligned load and store 2020-02-19 12:02:27 +01:00
NVPTX [NVPTX, LSV] Move the LSV optimization pass to later when the graph is cleaner 2020-02-13 12:15:38 -08:00
PowerPC [TargetLowering] SimplifyDemandedBits - fix SCALAR_TO_VECTOR knownbits bug 2020-02-28 15:23:37 +00:00
RISCV [RISCV] Compress instructions based on function features 2020-02-28 11:52:55 +00:00
SPARC Emit register names in cfi assembly directives 2020-02-25 14:00:01 -05:00
SystemZ [LegalizeTypes] Scalarize non-byte sized loads in WidenRecRes_Load and SplitVecResLoad 2020-02-24 15:14:33 -08:00
Thumb [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
Thumb2 Revert "[NFC][ARM] Update test" 2020-02-28 09:14:50 -08:00
VE [VE] TLS codegen 2020-02-18 16:09:12 +01:00
WebAssembly [WebAssembly] Simplify extract_vector lowering 2020-02-25 13:54:48 -08:00
WinCFGuard
WinEH
X86 [X86] Recognize CVTPH2PS from STRICT_FP_EXTEND 2020-02-28 10:19:57 -08:00
XCore [XCore] Add instruction pattern for bitrev 2020-02-21 09:28:49 +08:00