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Simon Cook ca950a6bb1 [RISCV] Compress instructions based on function features 
When running under LTO, it is common to not specify the architecture
spec, which is used for setting up the target machine, and instead rely
on features specified in each function to generate the correct
instructions.

This works for the code generator, but the RISC-V backend uses the
AsmPrinter to do instruction compression, which does not see these
features but instead uses a MCSubtargetInfo object to see whether
compression is enabled. Since this is configured based on the
TargetMachine at startup, it will result in compressed instructions not
being emitted when it has not been given the 'c' TargetFeature, but the
function has it.

This changes the RISCVAsmPrinter to re-initialize the STI feature set
based on the current MachineFunction, such that compressed instructions
are now correctly emitted regardless of the method used to enable them.

Differential revision: https://reviews.llvm.org/D73339
 		2020-02-28 11:52:55 +00:00
..
GlobalISel [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
intrinsics [RISCV] Lower llvm.trap and llvm.debugtrap 2019-10-28 09:54:33 +00:00
add-before-shl.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addc-adde-sube-subc.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addcarry.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
align.ll
…
alloca.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
alu8.ll
…
alu16.ll
…
alu32.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
alu64.ll Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. 2019-12-05 14:32:11 +08:00
analyze-branch.ll
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arith-with-overflow.ll [TargetLowering] Simplify expansion of S{ADD,SUB}O 2019-09-30 07:58:50 +00:00
atomic-cmpxchg-flag.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
atomic-cmpxchg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll [MBP] Avoid tail duplication if it can't bring benefit 2019-12-06 09:53:53 -08:00
bare-select.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
blockaddress.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
branch-relaxation.ll [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
branch.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
byval.ll
…
callee-saved-fpr32s.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
callee-saved-fpr64s.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
callee-saved-gprs.ll [RISCV] Remove RA from reserved register to use as callee saved register 2019-10-29 11:32:16 +08:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32d.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-lp64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-rv32f-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-sext-zext.ll
…
calls.ll [RISCV] Lower calls through PLT 2019-06-18 14:29:45 +00:00
codemodel-lowering.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
compress-float.ll [RISCV] Compress instructions based on function features 2020-02-28 11:52:55 +00:00
compress-inline-asm.ll [RISCV] Support llvm-objdump -M no-aliases and -M numeric 2019-09-10 16:24:03 +00:00
compress.ll [RISCV] Compress instructions based on function features 2020-02-28 11:52:55 +00:00
copysign-casts.ll [LegalizeTypes][RISCV] Soften FCOPYSIGN operand 2019-11-26 15:22:55 +00:00
disable-tail-calls.ll
…
disjoint.ll [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook 2019-11-05 09:39:06 +00:00
div.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-arith.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-bitmanip-dagcombines.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-br-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-calling-conv.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-frem.ll
…
double-imm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-previous-failure.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-stack-spill-restore.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
dwarf-eh.ll [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll 2019-07-17 14:04:48 +00:00
exception-pointer-register.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
fastcc-float.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fastcc-int.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fixups-diff.ll
…
fixups-relax-diff.ll [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. 2019-07-19 02:03:34 +00:00
float-arith.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-bit-preserving-dagcombines.ll [RISCV] Support Bit-Preserving FP in F/D Extensions 2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-frem.ll
…
float-imm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
flt-rounds.ll
…
fp16-promote.ll [RISCV] Add support for half-precision floats 2019-10-25 14:02:02 +01:00
fp128.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
frame-info.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
frame.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
frameaddr-returnaddr.ll
…
get-register-invalid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
get-register-noreserve.ll [RISCV] Implement the TargetLowering::getRegisterByName hook 2019-11-04 11:23:54 +00:00
get-register-reserve.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
get-setcc-result-type.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
hoist-global-addr-base.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
i32-icmp.ll [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
imm-cse.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
imm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
indirectbr.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
init-array.ll [IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format 2019-05-15 02:35:32 +00:00
inline-asm-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-clobbers.ll [RISCV] Add support for lowering floating point inlineasm clobbers 2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-f-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-i-constraint-i1.ll [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll Emit diagnostic if an inline asm constraint requires an immediate 2019-08-03 05:52:47 +00:00
inline-asm.ll [RISCV] Fix test for inline asm z constraint modifier 2020-01-15 13:50:50 +00:00
interrupt-attr-args-error.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr-callee.ll [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler 2020-02-15 09:14:04 +08:00
interrupt-attr-invalid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr-nocall.ll Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
interrupt-attr-ret-error.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr.ll Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
jumptable.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
large-stack.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
legalize-fneg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
machineoutliner.mir [RISCV] Enable the machine outliner for RISC-V 2019-12-19 16:41:53 +00:00
mattr-invalid-combination.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mem64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mir-target-flags.ll [RISCV] Fix mir-target-flags.ll 2019-12-09 13:51:08 +00:00
module-target-abi.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
module-target-abi2.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
mul.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
musttail-call.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
option-norelax.ll
…
option-norvc.ll [RISCV] Support llvm-objdump -M no-aliases and -M numeric 2019-09-10 16:24:03 +00:00
option-relax.ll
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option-rvc.ll [RISCV] Support llvm-objdump -M no-aliases and -M numeric 2019-09-10 16:24:03 +00:00
pic-models.ll [RISCV] Add lowering of addressing sequences for PIC 2019-06-11 12:57:47 +00:00
pr40333.ll
…
prefetch.ll
…
readcyclecounter.ll [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
rem.ll
…
remat.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
reserved-reg-errors.ll [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
reserved-regs.ll [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
rotl-rotr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv32e.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
rv32i-rv64i-float-double.ll [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 2019-08-28 23:40:37 +00:00
rv64-large-stack.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
rv64d-double-convert.ll
…
rv64f-float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-complex-float.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64i-single-softfloat.ll [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 2019-08-28 23:40:37 +00:00
rv64i-tricky-shifts.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv64i-w-insts-legalization.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
saverestore.ll [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
sdata-limit-0.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-4.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-8.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-local-sym.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
select-cc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
select-optimize-multiple.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
setcc-logic.ll [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
sext-zext-trunc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
…
shifts.ll Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. 2019-12-05 14:32:11 +08:00
shrinkwrap.ll [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
split-offsets.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
split-sp-adjust.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
srem-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
srem-vector-lkk.ll [TargetLowering] SimplifyDemandedBits - Remove ashr if all our demandedbits already match the sign bit 2020-01-25 17:36:46 +00:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Handle variable sized objects with the stack need to be realigned 2019-11-16 12:39:53 +08:00
stack-realignment.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
subtarget-features-std-ext.ll [RISCV] Support ABI checking with per function target-features 2020-01-22 08:12:28 -08:00
tail-calls.ll [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization 2020-02-18 23:56:42 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
tls-models.ll [RISCV] Don't force Local Exec TLS for non-PIC 2019-12-03 22:04:54 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
urem-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
urem-vector-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
vararg.ll [RISCV] Fix incorrect FP base CFI offset for variable argument functions 2020-02-10 11:56:08 +08:00
verify-instr.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
wide-mem.ll
…
zext-with-load-is-free.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00