93 lines
3.0 KiB
TableGen
93 lines
3.0 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s
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//
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// CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Test::subreg_hh32 or Test::subreg_h32
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// CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::subreg_ll32 or Test::subreg_l32
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include "llvm/Target/Target.td"
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def TestInstrInfo : InstrInfo {
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}
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def Test : Target {
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let InstructionSet = TestInstrInfo;
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}
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let Namespace = "Test" in {
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def subreg_l32 : SubRegIndex<32, 0>;
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def subreg_h32 : SubRegIndex<32, 32>;
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def subreg_h64 : SubRegIndex<64, 64>;
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def subreg_l64 : SubRegIndex<64, 0>;
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def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>;
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def subreg_ll32 : ComposedSubRegIndex<subreg_l64, subreg_l32>;
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}
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class TestReg<string n, list<Register> s> : RegisterWithSubRegs<n, s> {
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let Namespace = "Test";
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}
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// --------------------------------------------------------------------
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// A situation that previously caused the warning about ambiguous
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// composition.
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//
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// The actual subregister actions are:
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// subreg_h64: { F0Q->F0D V0Q->F0D }
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// subreg_h32: { F0D->F0S F0Q->F2S V0Q->F0S }
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// composition: { F0Q->F0S V0Q->F0S } (this is the same as subreg_hh32)
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//
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// For the register V0Q, subreg_hh32(V0Q) = subreg_h32(V0Q) = F0S, which
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// would be enough to trigger the warning about ambiguous composition.
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// However, for F0Q, subreg_hh32(F0Q) = F0S, while subreg_h32(F0Q) = F2S,
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// which shows that there two subregister indices are different.
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// Make sure that the warning is not emitted in this case.
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class FPR32<string n> : TestReg<n, []> {
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}
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class FPR64<string n, FPR32 high> : TestReg<n, [high]> {
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let SubRegIndices = [subreg_h32];
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}
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class FPR128<string n, FPR64 high, FPR32 low> : TestReg<n, [high, low]> {
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let SubRegIndices = [subreg_h64, subreg_h32];
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}
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class VPR128<string n, FPR64 high> : TestReg<n, [high]> {
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let SubRegIndices = [subreg_h64];
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}
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def F0S : FPR32<"f0s">;
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def F1S : FPR32<"f1s">;
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def F2S : FPR32<"f2s">;
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def F0D : FPR64<"f0d", F0S>;
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def F0Q : FPR128<"f0q", F0D, F2S>;
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def V0Q : VPR128<"v0q", F0D>;
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def FP32 : RegisterClass<"FP32", [f32], 32, (add F0S)>;
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def FP64 : RegisterClass<"FP64", [f64], 64, (add F0D)>;
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def FP128 : RegisterClass<"FP128", [v2f64], 128, (add F0Q)>;
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def VP128 : RegisterClass<"VP128", [v2f64], 128, (add V0Q)>;
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// --------------------------------------------------------------------
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// A situation where the warning is legitimate.
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// Make sure that the warning is still displayed.
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class GPR32<string n> : TestReg<n, []> {
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}
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class GPR64<string n, GPR32 low> : TestReg<n, [low]> {
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let SubRegIndices = [subreg_l32];
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}
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class GPR128<string n, GPR64 low> : TestReg<n, [low]> {
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let SubRegIndices = [subreg_l64];
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}
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def G0S : GPR32<"g0s">;
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def G0D : GPR64<"g0d", G0S>;
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def G0Q : GPR128<"g0q", G0D>;
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def GP32 : RegisterClass<"GP32", [i32], 32, (add G0S)>;
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def GP64 : RegisterClass<"GP64", [i64], 64, (add G0D)>;
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def GP128 : RegisterClass<"GP128", [v2i64], 128, (add G0Q)>;
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