llvm-project/llvm/lib/Target/Sparc
David Green ca29c271d2 [Targets] Add errors for tiny and kernel codemodel on targets that don't support them
Adds fatal errors for any target that does not support the Tiny or Kernel
codemodels by rejigging the getEffectiveCodeModel calls.

Differential Revision: https://reviews.llvm.org/D50141

llvm-svn: 348585
2018-12-07 12:10:23 +00:00
..
AsmParser Remove trailing space 2018-07-30 19:41:25 +00:00
Disassembler [Target] Untangle disassemblers 2018-09-10 12:53:46 +00:00
InstPrinter Remove trailing space 2018-07-30 19:41:25 +00:00
MCTargetDesc [Sparc] Move SparcTargetStreamer.h to the MC Desc, where the implementation is already 2018-09-10 13:55:38 +00:00
TargetInfo
CMakeLists.txt Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt 2018-04-23 12:49:34 +00:00
DelaySlotFiller.cpp [DebugInfo] Examine all uses of isDebugValue() for debug instructions. 2018-05-09 02:42:00 +00:00
LLVMBuild.txt
LeonFeatures.td [Sparc] Add support for the cycle counter available in GR740 2018-08-27 11:11:47 +00:00
LeonPasses.cpp
LeonPasses.h
README.txt
Sparc.h Remove trailing space 2018-07-30 19:41:25 +00:00
Sparc.td [Sparc] Add support for the partial write PSR instruction 2018-09-27 12:34:48 +00:00
SparcAsmPrinter.cpp [Sparc] Move SparcTargetStreamer.h to the MC Desc, where the implementation is already 2018-09-10 13:55:38 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp [Sparc] Account for bias in stack readjustment 2018-01-29 12:10:32 +00:00
SparcFrameLowering.h
SparcISelDAGToDAG.cpp Revert "This pass, fixing an erratum in some LEON 2 processors..." 2018-04-20 07:53:27 +00:00
SparcISelLowering.cpp [Sparc] Remove the support for builtin setjmp/longjmp 2018-09-27 13:32:54 +00:00
SparcISelLowering.h [Sparc] Remove the support for builtin setjmp/longjmp 2018-09-27 13:32:54 +00:00
SparcInstr64Bit.td [Sparc] allow tls_add/tls_call syntax in assembler parser 2018-09-03 10:38:12 +00:00
SparcInstrAliases.td [Sparc] Add unimp alias 2018-09-27 12:34:53 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp Remove trailing space 2018-07-30 19:41:25 +00:00
SparcInstrInfo.h
SparcInstrInfo.td [Sparc] Remove the support for builtin setjmp/longjmp 2018-09-27 13:32:54 +00:00
SparcInstrVIS.td
SparcMCInstLower.cpp
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp [Sparc] Add support for the cycle counter available in GR740 2018-08-27 11:11:47 +00:00
SparcRegisterInfo.h [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() 2018-10-05 14:23:11 +00:00
SparcRegisterInfo.td
SparcSchedule.td
SparcSubtarget.cpp [Sparc] Add support for the partial write PSR instruction 2018-09-27 12:34:48 +00:00
SparcSubtarget.h [Sparc] Add support for the partial write PSR instruction 2018-09-27 12:34:48 +00:00
SparcTargetMachine.cpp [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00
SparcTargetMachine.h [Sparc] EXPENSIVE_CHECKS now passes all machine verifier errors (PR27461) 2018-09-27 16:21:35 +00:00
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.