116 lines
3.9 KiB
C++
116 lines
3.9 KiB
C++
//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about RISCV target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetMachine.h"
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#include "RISCV.h"
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#include "RISCVTargetObjectFile.h"
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#include "RISCVTargetTransformInfo.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
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auto PR = PassRegistry::getPassRegistry();
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initializeRISCVExpandPseudoPass(*PR);
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}
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static StringRef computeDataLayout(const Triple &TT) {
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if (TT.isArch64Bit()) {
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return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
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} else {
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assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
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return "e-m:e-p:32:32-i64:64-n32-S128";
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}
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(make_unique<RISCVELFTargetObjectFile>()),
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Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
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initAsmInfo();
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}
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TargetTransformInfo
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RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
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return TargetTransformInfo(RISCVTTIImpl(this, F));
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}
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namespace {
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class RISCVPassConfig : public TargetPassConfig {
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public:
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RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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RISCVTargetMachine &getRISCVTargetMachine() const {
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return getTM<RISCVTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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void addPreEmitPass2() override;
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void addPreRegAlloc() override;
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};
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}
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TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new RISCVPassConfig(*this, PM);
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}
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void RISCVPassConfig::addIRPasses() {
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addPass(createAtomicExpandPass());
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TargetPassConfig::addIRPasses();
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}
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bool RISCVPassConfig::addInstSelector() {
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addPass(createRISCVISelDag(getRISCVTargetMachine()));
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return false;
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}
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void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
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void RISCVPassConfig::addPreEmitPass2() {
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// Schedule the expansion of AMOs at the last possible moment, avoiding the
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// possibility for other passes to break the requirements for forward
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// progress in the LR/SC block.
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addPass(createRISCVExpandPseudoPass());
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}
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void RISCVPassConfig::addPreRegAlloc() {
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addPass(createRISCVMergeBaseOffsetOptPass());
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}
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