732 lines
22 KiB
TableGen
732 lines
22 KiB
TableGen
//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction defs that are common to all hw codegen
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// targets.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm = "",
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list<dag> pattern = []> : Instruction {
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field bit isRegisterLoad = 0;
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field bit isRegisterStore = 0;
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = NullALU;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<64> SoftFail = 0;
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let DecoderNamespace = Namespace;
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let TSFlags{63} = isRegisterLoad;
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let TSFlags{62} = isRegisterStore;
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm = "",
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list<dag> pattern = []> : AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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def FP16Denormals : Predicate<"Subtarget.hasFP16Denormals()">;
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def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
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def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
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def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
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def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
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def u16ImmTarget : AsmOperandClass {
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let Name = "U16Imm";
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let RenderMethod = "addImmOperands";
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}
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def s16ImmTarget : AsmOperandClass {
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let Name = "S16Imm";
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let RenderMethod = "addImmOperands";
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}
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let OperandType = "OPERAND_IMMEDIATE" in {
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def u32imm : Operand<i32> {
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let PrintMethod = "printU32ImmOperand";
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}
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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let ParserMatchClass = u16ImmTarget;
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}
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def s16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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let ParserMatchClass = s16ImmTarget;
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}
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def u8imm : Operand<i8> {
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let PrintMethod = "printU8ImmOperand";
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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//===--------------------------------------------------------------------===//
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// Custom Operands
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//===--------------------------------------------------------------------===//
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def brtarget : Operand<OtherVT>;
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//===----------------------------------------------------------------------===//
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// Misc. PatFrags
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//===----------------------------------------------------------------------===//
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class HasOneUseUnaryOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0),
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(op $src0),
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[{ return N->hasOneUse(); }]
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>;
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class HasOneUseBinOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1),
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(op $src0, $src1),
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[{ return N->hasOneUse(); }]
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>;
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class HasOneUseTernaryOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1, node:$src2),
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(op $src0, $src1, $src2),
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[{ return N->hasOneUse(); }]
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>;
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def trunc_oneuse : HasOneUseUnaryOp<trunc>;
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let Properties = [SDNPCommutative, SDNPAssociative] in {
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def smax_oneuse : HasOneUseBinOp<smax>;
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def smin_oneuse : HasOneUseBinOp<smin>;
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def umax_oneuse : HasOneUseBinOp<umax>;
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def umin_oneuse : HasOneUseBinOp<umin>;
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def fminnum_oneuse : HasOneUseBinOp<fminnum>;
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def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>;
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def and_oneuse : HasOneUseBinOp<and>;
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def or_oneuse : HasOneUseBinOp<or>;
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def xor_oneuse : HasOneUseBinOp<xor>;
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} // Properties = [SDNPCommutative, SDNPAssociative]
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def sub_oneuse : HasOneUseBinOp<sub>;
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def srl_oneuse : HasOneUseBinOp<srl>;
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def shl_oneuse : HasOneUseBinOp<shl>;
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def select_oneuse : HasOneUseTernaryOp<select>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for floating-point comparisons
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//===----------------------------------------------------------------------===//
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def COND_OEQ : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
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>;
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def COND_ONE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
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>;
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def COND_OGT : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
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>;
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def COND_OGE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
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>;
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def COND_OLT : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
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>;
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def COND_OLE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
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>;
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def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
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def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for unsigned / unordered comparisons
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//===----------------------------------------------------------------------===//
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def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
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def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
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def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
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def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
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def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
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def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
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// XXX - For some reason R600 version is preferring to use unordered
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// for setne?
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def COND_UNE_NE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
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>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for signed comparisons
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//===----------------------------------------------------------------------===//
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def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
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def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
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def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
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def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for integer equality
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//===----------------------------------------------------------------------===//
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def COND_EQ : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
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>;
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def COND_NE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
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>;
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def COND_NULL : PatLeaf <
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(cond),
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[{(void)N; return false;}]
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>;
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//===----------------------------------------------------------------------===//
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// Load/Store Pattern Fragments
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//===----------------------------------------------------------------------===//
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class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.PRIVATE_ADDRESS;
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}]>;
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class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
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(ops node:$ptr), (op node:$ptr)
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>;
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class PrivateStore <SDPatternOperator op> : PrivateMemOp <
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(ops node:$value, node:$ptr), (op node:$value, node:$ptr)
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>;
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def load_private : PrivateLoad <load>;
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def truncstorei8_private : PrivateStore <truncstorei8>;
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def truncstorei16_private : PrivateStore <truncstorei16>;
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def store_private : PrivateStore <store>;
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class GlobalMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS;
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}]>;
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// Global address space loads
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class GlobalLoad <SDPatternOperator op> : GlobalMemOp <
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(ops node:$ptr), (op node:$ptr)
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>;
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def global_load : GlobalLoad <load>;
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def global_atomic_load : GlobalLoad<atomic_load>;
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// Global address space stores
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class GlobalStore <SDPatternOperator op> : GlobalMemOp <
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(ops node:$value, node:$ptr), (op node:$value, node:$ptr)
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>;
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def global_store : GlobalStore <store>;
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def global_store_atomic : GlobalStore<atomic_store>;
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class ConstantMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS;
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}]>;
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// Constant address space loads
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class ConstantLoad <SDPatternOperator op> : ConstantMemOp <
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(ops node:$ptr), (op node:$ptr)
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>;
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def constant_load : ConstantLoad<load>;
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class LocalMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS;
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}]>;
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// Local address space loads
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class LocalLoad <SDPatternOperator op> : LocalMemOp <
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(ops node:$ptr), (op node:$ptr)
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>;
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class LocalStore <SDPatternOperator op> : LocalMemOp <
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(ops node:$value, node:$ptr), (op node:$value, node:$ptr)
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>;
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class FlatMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAddressSPace() == AMDGPUASI.FLAT_ADDRESS;
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}]>;
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class FlatLoad <SDPatternOperator op> : FlatMemOp <
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(ops node:$ptr), (op node:$ptr)
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>;
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class AZExtLoadBase <SDPatternOperator ld_node>: PatFrag<(ops node:$ptr),
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(ld_node node:$ptr), [{
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LoadSDNode *L = cast<LoadSDNode>(N);
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return L->getExtensionType() == ISD::ZEXTLOAD ||
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L->getExtensionType() == ISD::EXTLOAD;
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}]>;
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def az_extload : AZExtLoadBase <unindexedload>;
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def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def az_extloadi8_global : GlobalLoad <az_extloadi8>;
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def sextloadi8_global : GlobalLoad <sextloadi8>;
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def az_extloadi8_constant : ConstantLoad <az_extloadi8>;
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def sextloadi8_constant : ConstantLoad <sextloadi8>;
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def az_extloadi8_local : LocalLoad <az_extloadi8>;
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def sextloadi8_local : LocalLoad <sextloadi8>;
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def extloadi8_private : PrivateLoad <az_extloadi8>;
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def sextloadi8_private : PrivateLoad <sextloadi8>;
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def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def az_extloadi16_global : GlobalLoad <az_extloadi16>;
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def sextloadi16_global : GlobalLoad <sextloadi16>;
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def az_extloadi16_constant : ConstantLoad <az_extloadi16>;
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def sextloadi16_constant : ConstantLoad <sextloadi16>;
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def az_extloadi16_local : LocalLoad <az_extloadi16>;
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def sextloadi16_local : LocalLoad <sextloadi16>;
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def extloadi16_private : PrivateLoad <az_extloadi16>;
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def sextloadi16_private : PrivateLoad <sextloadi16>;
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def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def az_extloadi32_global : GlobalLoad <az_extloadi32>;
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def az_extloadi32_flat : FlatLoad <az_extloadi32>;
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def az_extloadi32_constant : ConstantLoad <az_extloadi32>;
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def truncstorei8_global : GlobalStore <truncstorei8>;
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def truncstorei16_global : GlobalStore <truncstorei16>;
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def local_store : LocalStore <store>;
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def truncstorei8_local : LocalStore <truncstorei8>;
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def truncstorei16_local : LocalStore <truncstorei16>;
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def local_load : LocalLoad <load>;
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class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
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}]>;
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def local_load_aligned8bytes : Aligned8Bytes <
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(ops node:$ptr), (local_load node:$ptr)
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>;
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def local_store_aligned8bytes : Aligned8Bytes <
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(ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
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>;
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class local_binary_atomic_op<SDNode atomic_op> :
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PatFrag<(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value), [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS;
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}]>;
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def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
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def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
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def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
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def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
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def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
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def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
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def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
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def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
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def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
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def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
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def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
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def mskor_global : PatFrag<(ops node:$val, node:$ptr),
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(AMDGPUstore_mskor node:$val, node:$ptr), [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS;
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}]>;
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multiclass AtomicCmpSwapLocal <SDNode cmp_swap_node> {
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def _32_local : PatFrag <
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(ops node:$ptr, node:$cmp, node:$swap),
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(cmp_swap_node node:$ptr, node:$cmp, node:$swap), [{
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AtomicSDNode *AN = cast<AtomicSDNode>(N);
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return AN->getMemoryVT() == MVT::i32 &&
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AN->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS;
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}]>;
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def _64_local : PatFrag<
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(ops node:$ptr, node:$cmp, node:$swap),
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(cmp_swap_node node:$ptr, node:$cmp, node:$swap), [{
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AtomicSDNode *AN = cast<AtomicSDNode>(N);
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return AN->getMemoryVT() == MVT::i64 &&
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AN->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS;
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}]>;
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}
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defm atomic_cmp_swap : AtomicCmpSwapLocal <atomic_cmp_swap>;
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multiclass global_binary_atomic_op<SDNode atomic_op> {
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def "" : PatFrag<
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(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS;}]>;
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def _noret : PatFrag<
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(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;
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def _ret : PatFrag<
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(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;
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}
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defm atomic_swap_global : global_binary_atomic_op<atomic_swap>;
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defm atomic_add_global : global_binary_atomic_op<atomic_load_add>;
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defm atomic_and_global : global_binary_atomic_op<atomic_load_and>;
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defm atomic_max_global : global_binary_atomic_op<atomic_load_max>;
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defm atomic_min_global : global_binary_atomic_op<atomic_load_min>;
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defm atomic_or_global : global_binary_atomic_op<atomic_load_or>;
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defm atomic_sub_global : global_binary_atomic_op<atomic_load_sub>;
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defm atomic_umax_global : global_binary_atomic_op<atomic_load_umax>;
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defm atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
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defm atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
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//legacy
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def AMDGPUatomic_cmp_swap_global : PatFrag<
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(ops node:$ptr, node:$value),
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(AMDGPUatomic_cmp_swap node:$ptr, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS;}]>;
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def atomic_cmp_swap_global : PatFrag<
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(ops node:$ptr, node:$cmp, node:$value),
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(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS;}]>;
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def atomic_cmp_swap_global_noret : PatFrag<
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(ops node:$ptr, node:$cmp, node:$value),
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(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;
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def atomic_cmp_swap_global_ret : PatFrag<
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(ops node:$ptr, node:$cmp, node:$value),
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(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Misc Pattern Fragments
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Constants {
|
|
int TWO_PI = 0x40c90fdb;
|
|
int PI = 0x40490fdb;
|
|
int TWO_PI_INV = 0x3e22f983;
|
|
int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
|
|
int FP16_ONE = 0x3C00;
|
|
int V2FP16_ONE = 0x3C003C00;
|
|
int FP32_ONE = 0x3f800000;
|
|
int FP32_NEG_ONE = 0xbf800000;
|
|
int FP64_ONE = 0x3ff0000000000000;
|
|
int FP64_NEG_ONE = 0xbff0000000000000;
|
|
}
|
|
def CONST : Constants;
|
|
|
|
def FP_ZERO : PatLeaf <
|
|
(fpimm),
|
|
[{return N->getValueAPF().isZero();}]
|
|
>;
|
|
|
|
def FP_ONE : PatLeaf <
|
|
(fpimm),
|
|
[{return N->isExactlyValue(1.0);}]
|
|
>;
|
|
|
|
def FP_HALF : PatLeaf <
|
|
(fpimm),
|
|
[{return N->isExactlyValue(0.5);}]
|
|
>;
|
|
|
|
let isCodeGenOnly = 1, isPseudo = 1 in {
|
|
|
|
let usesCustomInserter = 1 in {
|
|
|
|
class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
|
|
(outs rc:$dst),
|
|
(ins rc:$src0),
|
|
"CLAMP $dst, $src0",
|
|
[(set f32:$dst, (AMDGPUclamp f32:$src0))]
|
|
>;
|
|
|
|
class FABS <RegisterClass rc> : AMDGPUShaderInst <
|
|
(outs rc:$dst),
|
|
(ins rc:$src0),
|
|
"FABS $dst, $src0",
|
|
[(set f32:$dst, (fabs f32:$src0))]
|
|
>;
|
|
|
|
class FNEG <RegisterClass rc> : AMDGPUShaderInst <
|
|
(outs rc:$dst),
|
|
(ins rc:$src0),
|
|
"FNEG $dst, $src0",
|
|
[(set f32:$dst, (fneg f32:$src0))]
|
|
>;
|
|
|
|
} // usesCustomInserter = 1
|
|
|
|
multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
|
|
ComplexPattern addrPat> {
|
|
let UseNamedOperandTable = 1 in {
|
|
|
|
def RegisterLoad : AMDGPUShaderInst <
|
|
(outs dstClass:$dst),
|
|
(ins addrClass:$addr, i32imm:$chan),
|
|
"RegisterLoad $dst, $addr",
|
|
[(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
|
|
> {
|
|
let isRegisterLoad = 1;
|
|
}
|
|
|
|
def RegisterStore : AMDGPUShaderInst <
|
|
(outs),
|
|
(ins dstClass:$val, addrClass:$addr, i32imm:$chan),
|
|
"RegisterStore $val, $addr",
|
|
[(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
|
|
> {
|
|
let isRegisterStore = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
} // End isCodeGenOnly = 1, isPseudo = 1
|
|
|
|
/* Generic helper patterns for intrinsics */
|
|
/* -------------------------------------- */
|
|
|
|
class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
|
|
: Pat <
|
|
(fpow f32:$src0, f32:$src1),
|
|
(exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
|
|
>;
|
|
|
|
/* Other helper patterns */
|
|
/* --------------------- */
|
|
|
|
/* Extract element pattern */
|
|
class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
|
|
SubRegIndex sub_reg>
|
|
: Pat<
|
|
(sub_type (extractelt vec_type:$src, sub_idx)),
|
|
(EXTRACT_SUBREG $src, sub_reg)
|
|
>;
|
|
|
|
/* Insert element pattern */
|
|
class Insert_Element <ValueType elem_type, ValueType vec_type,
|
|
int sub_idx, SubRegIndex sub_reg>
|
|
: Pat <
|
|
(insertelt vec_type:$vec, elem_type:$elem, sub_idx),
|
|
(INSERT_SUBREG $vec, $elem, sub_reg)
|
|
>;
|
|
|
|
// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
|
|
// can handle COPY instructions.
|
|
// bitconvert pattern
|
|
class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
|
|
(dt (bitconvert (st rc:$src0))),
|
|
(dt rc:$src0)
|
|
>;
|
|
|
|
// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
|
|
// can handle COPY instructions.
|
|
class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
|
|
(vt (AMDGPUdwordaddr (vt rc:$addr))),
|
|
(vt rc:$addr)
|
|
>;
|
|
|
|
// BFI_INT patterns
|
|
|
|
multiclass BFIPatterns <Instruction BFI_INT,
|
|
Instruction LoadImm32,
|
|
RegisterClass RC64> {
|
|
// Definition from ISA doc:
|
|
// (y & x) | (z & ~x)
|
|
def : Pat <
|
|
(or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
|
|
(BFI_INT $x, $y, $z)
|
|
>;
|
|
|
|
// SHA-256 Ch function
|
|
// z ^ (x & (y ^ z))
|
|
def : Pat <
|
|
(xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
|
|
(BFI_INT $x, $y, $z)
|
|
>;
|
|
|
|
def : Pat <
|
|
(fcopysign f32:$src0, f32:$src1),
|
|
(BFI_INT (LoadImm32 (i32 0x7fffffff)), $src0, $src1)
|
|
>;
|
|
|
|
def : Pat <
|
|
(f32 (fcopysign f32:$src0, f64:$src1)),
|
|
(BFI_INT (LoadImm32 (i32 0x7fffffff)), $src0,
|
|
(i32 (EXTRACT_SUBREG $src1, sub1)))
|
|
>;
|
|
|
|
def : Pat <
|
|
(f64 (fcopysign f64:$src0, f64:$src1)),
|
|
(REG_SEQUENCE RC64,
|
|
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
|
|
(BFI_INT (LoadImm32 (i32 0x7fffffff)),
|
|
(i32 (EXTRACT_SUBREG $src0, sub1)),
|
|
(i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
|
|
>;
|
|
|
|
def : Pat <
|
|
(f64 (fcopysign f64:$src0, f32:$src1)),
|
|
(REG_SEQUENCE RC64,
|
|
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
|
|
(BFI_INT (LoadImm32 (i32 0x7fffffff)),
|
|
(i32 (EXTRACT_SUBREG $src0, sub1)),
|
|
$src1), sub1)
|
|
>;
|
|
}
|
|
|
|
// SHA-256 Ma patterns
|
|
|
|
// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
|
|
class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
|
|
(or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
|
|
(BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
|
|
>;
|
|
|
|
// Bitfield extract patterns
|
|
|
|
def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
|
|
return isMask_32(N->getZExtValue());
|
|
}]>;
|
|
|
|
def IMMPopCount : SDNodeXForm<imm, [{
|
|
return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
|
|
MVT::i32);
|
|
}]>;
|
|
|
|
multiclass BFEPattern <Instruction UBFE, Instruction SBFE, Instruction MOV> {
|
|
def : Pat <
|
|
(i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
|
|
(UBFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
|
|
>;
|
|
|
|
def : Pat <
|
|
(srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
|
|
(UBFE $src, (i32 0), $width)
|
|
>;
|
|
|
|
def : Pat <
|
|
(sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
|
|
(SBFE $src, (i32 0), $width)
|
|
>;
|
|
}
|
|
|
|
// rotr pattern
|
|
class ROTRPattern <Instruction BIT_ALIGN> : Pat <
|
|
(rotr i32:$src0, i32:$src1),
|
|
(BIT_ALIGN $src0, $src0, $src1)
|
|
>;
|
|
|
|
// This matches 16 permutations of
|
|
// max(min(x, y), min(max(x, y), z))
|
|
class IntMed3Pat<Instruction med3Inst,
|
|
SDPatternOperator max,
|
|
SDPatternOperator max_oneuse,
|
|
SDPatternOperator min_oneuse,
|
|
ValueType vt = i32> : Pat<
|
|
(max (min_oneuse vt:$src0, vt:$src1),
|
|
(min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)),
|
|
(med3Inst $src0, $src1, $src2)
|
|
>;
|
|
|
|
// Special conversion patterns
|
|
|
|
def cvt_rpi_i32_f32 : PatFrag <
|
|
(ops node:$src),
|
|
(fp_to_sint (ffloor (fadd $src, FP_HALF))),
|
|
[{ (void) N; return TM.Options.NoNaNsFPMath; }]
|
|
>;
|
|
|
|
def cvt_flr_i32_f32 : PatFrag <
|
|
(ops node:$src),
|
|
(fp_to_sint (ffloor $src)),
|
|
[{ (void)N; return TM.Options.NoNaNsFPMath; }]
|
|
>;
|
|
|
|
class IMad24Pat<Instruction Inst> : Pat <
|
|
(add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
|
|
(Inst $src0, $src1, $src2)
|
|
>;
|
|
|
|
class UMad24Pat<Instruction Inst> : Pat <
|
|
(add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
|
|
(Inst $src0, $src1, $src2)
|
|
>;
|
|
|
|
class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
|
|
(fdiv FP_ONE, vt:$src),
|
|
(RcpInst $src)
|
|
>;
|
|
|
|
class RsqPat<Instruction RsqInst, ValueType vt> : Pat <
|
|
(AMDGPUrcp (fsqrt vt:$src)),
|
|
(RsqInst $src)
|
|
>;
|
|
|
|
include "R600Instructions.td"
|
|
include "R700Instructions.td"
|
|
include "EvergreenInstructions.td"
|
|
include "CaymanInstructions.td"
|
|
|
|
include "SIInstrInfo.td"
|
|
|