367 lines
13 KiB
C++
367 lines
13 KiB
C++
//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#include "AMDGPU.h"
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#include "AMDKernelCodeT.h"
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#include "SIDefines.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cstdint>
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#include <utility>
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namespace llvm {
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class Argument;
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class FeatureBitset;
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class Function;
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class GlobalValue;
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class MachineMemOperand;
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class MCContext;
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class MCRegisterClass;
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class MCRegisterInfo;
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class MCSection;
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class MCSubtargetInfo;
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class Triple;
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namespace AMDGPU {
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namespace IsaInfo {
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enum {
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// The closed Vulkan driver sets 96, which limits the wave count to 8 but
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// doesn't spill SGPRs as much as when 80 is set.
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FIXED_NUM_SGPRS_FOR_INIT_BUG = 96
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};
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/// \brief Instruction set architecture version.
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struct IsaVersion {
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unsigned Major;
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unsigned Minor;
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unsigned Stepping;
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};
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/// \returns Isa version for given subtarget \p Features.
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IsaVersion getIsaVersion(const FeatureBitset &Features);
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/// \returns Wavefront size for given subtarget \p Features.
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unsigned getWavefrontSize(const FeatureBitset &Features);
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/// \returns Local memory size in bytes for given subtarget \p Features.
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unsigned getLocalMemorySize(const FeatureBitset &Features);
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/// \returns Number of execution units per compute unit for given subtarget \p
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/// Features.
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unsigned getEUsPerCU(const FeatureBitset &Features);
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/// \returns Maximum number of work groups per compute unit for given subtarget
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/// \p Features and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns Maximum number of waves per compute unit for given subtarget \p
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/// Features without any kind of limitation.
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unsigned getMaxWavesPerCU(const FeatureBitset &Features);
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/// \returns Maximum number of waves per compute unit for given subtarget \p
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/// Features and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWavesPerCU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum number of waves per execution unit for given subtarget \p
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/// Features.
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unsigned getMinWavesPerEU(const FeatureBitset &Features);
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/// \returns Maximum number of waves per execution unit for given subtarget \p
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/// Features without any kind of limitation.
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unsigned getMaxWavesPerEU(const FeatureBitset &Features);
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/// \returns Maximum number of waves per execution unit for given subtarget \p
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/// Features and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWavesPerEU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum flat work group size for given subtarget \p Features.
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unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
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/// \returns Maximum flat work group size for given subtarget \p Features.
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unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
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/// \returns Number of waves per work group for given subtarget \p Features and
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/// limited by given \p FlatWorkGroupSize.
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unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns SGPR allocation granularity for given subtarget \p Features.
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unsigned getSGPRAllocGranule(const FeatureBitset &Features);
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/// \returns SGPR encoding granularity for given subtarget \p Features.
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unsigned getSGPREncodingGranule(const FeatureBitset &Features);
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/// \returns Total number of SGPRs for given subtarget \p Features.
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unsigned getTotalNumSGPRs(const FeatureBitset &Features);
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/// \returns Addressable number of SGPRs for given subtarget \p Features.
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unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
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/// \returns Minimum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
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/// \returns Maximum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
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bool Addressable);
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/// \returns VGPR allocation granularity for given subtarget \p Features.
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unsigned getVGPRAllocGranule(const FeatureBitset &Features);
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/// \returns VGPR encoding granularity for given subtarget \p Features.
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unsigned getVGPREncodingGranule(const FeatureBitset &Features);
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/// \returns Total number of VGPRs for given subtarget \p Features.
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unsigned getTotalNumVGPRs(const FeatureBitset &Features);
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/// \returns Addressable number of VGPRs for given subtarget \p Features.
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unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
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/// \returns Minimum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
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/// \returns Maximum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
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} // end namespace IsaInfo
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LLVM_READONLY
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features);
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bool isGroupSegment(const GlobalValue *GV, AMDGPUAS AS);
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bool isGlobalSegment(const GlobalValue *GV, AMDGPUAS AS);
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bool isReadOnlySegment(const GlobalValue *GV, AMDGPUAS AS);
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/// \returns True if constants should be emitted to .text section for given
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/// target triple \p TT, false otherwise.
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bool shouldEmitConstantsToTextSection(const Triple &TT);
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/// \returns Integer value requested using \p F's \p Name attribute.
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if requested value cannot be converted
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/// to integer.
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int getIntegerAttribute(const Function &F, StringRef Name, int Default);
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/// \returns A pair of integer values requested using \p F's \p Name attribute
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/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
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/// is false).
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if one of the requested values cannot be
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/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
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/// not present.
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired = false);
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/// \returns Vmcnt bit mask for given isa \p Version.
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unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
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/// \returns Expcnt bit mask for given isa \p Version.
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unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
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/// \returns Lgkmcnt bit mask for given isa \p Version.
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unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
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/// \returns Waitcnt bit mask for given isa \p Version.
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unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
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/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
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/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
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/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
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/// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
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/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
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/// \p Lgkmcnt respectively.
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///
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/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
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/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
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/// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
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/// \p Expcnt = \p Waitcnt[6:4]
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/// \p Lgkmcnt = \p Waitcnt[11:8]
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void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
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/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
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unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Vmcnt);
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/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
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unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Expcnt);
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/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
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unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Lgkmcnt);
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/// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
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/// \p Version.
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///
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/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
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/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
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/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
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/// Waitcnt[6:4] = \p Expcnt
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/// Waitcnt[11:8] = \p Lgkmcnt
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/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
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///
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/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
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/// isa \p Version.
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unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
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unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
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unsigned getInitialPSInputAddr(const Function &F);
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LLVM_READNONE
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bool isShader(CallingConv::ID CC);
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LLVM_READNONE
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bool isCompute(CallingConv::ID CC);
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LLVM_READNONE
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bool isEntryFunctionCC(CallingConv::ID CC);
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// FIXME: Remove this when calling conventions cleaned up
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LLVM_READNONE
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inline bool isKernel(CallingConv::ID CC) {
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switch (CC) {
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case CallingConv::AMDGPU_KERNEL:
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case CallingConv::SPIR_KERNEL:
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return true;
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default:
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return false;
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}
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}
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bool isSI(const MCSubtargetInfo &STI);
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bool isCI(const MCSubtargetInfo &STI);
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bool isVI(const MCSubtargetInfo &STI);
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bool isGFX9(const MCSubtargetInfo &STI);
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/// \brief Is Reg - scalar register
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bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
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/// \brief Is there any intersection between registers
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bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
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/// If \p Reg is a pseudo reg, return the correct hardware register given
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/// \p STI otherwise return \p Reg.
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unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
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/// \brief Convert hardware register \p Reg to a pseudo register
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LLVM_READNONE
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unsigned mc2PseudoReg(unsigned Reg);
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/// \brief Can this operand also contain immediate values?
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
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/// \brief Is this floating-point operand?
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bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
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/// \brief Does this opearnd support only inlinable literals?
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bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
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/// \brief Get the size in bits of a register from the register class \p RC.
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unsigned getRegBitWidth(unsigned RCID);
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/// \brief Get the size in bits of a register from the register class \p RC.
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unsigned getRegBitWidth(const MCRegisterClass &RC);
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/// \brief Get size of register operand
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unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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unsigned OpNo);
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LLVM_READNONE
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inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
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switch (OpInfo.OperandType) {
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case AMDGPU::OPERAND_REG_IMM_INT32:
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case AMDGPU::OPERAND_REG_IMM_FP32:
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case AMDGPU::OPERAND_REG_INLINE_C_INT32:
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case AMDGPU::OPERAND_REG_INLINE_C_FP32:
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return 4;
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case AMDGPU::OPERAND_REG_IMM_INT64:
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case AMDGPU::OPERAND_REG_IMM_FP64:
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case AMDGPU::OPERAND_REG_INLINE_C_INT64:
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case AMDGPU::OPERAND_REG_INLINE_C_FP64:
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return 8;
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case AMDGPU::OPERAND_REG_IMM_INT16:
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case AMDGPU::OPERAND_REG_IMM_FP16:
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case AMDGPU::OPERAND_REG_INLINE_C_INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_FP16:
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case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
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return 2;
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default:
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llvm_unreachable("unhandled operand type");
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}
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}
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LLVM_READNONE
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inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
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return getOperandSize(Desc.OpInfo[OpNo]);
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}
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/// \brief Is this literal inlinable
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LLVM_READNONE
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bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
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LLVM_READNONE
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bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
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LLVM_READNONE
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bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
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LLVM_READNONE
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bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
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bool isArgPassedInSGPR(const Argument *Arg);
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bool isUniformMMO(const MachineMemOperand *MMO);
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/// \returns The encoding that will be used for \p ByteOffset in the SMRD
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/// offset field.
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int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
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/// \returns true if this offset is small enough to fit in the SMRD
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/// offset field. \p ByteOffset should be the offset in bytes and
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/// not the encoded offset.
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bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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