1017 lines
55 KiB
TableGen
1017 lines
55 KiB
TableGen
//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget state.
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//
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def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode",
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"true", "Thumb mode">;
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def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
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"true", "Use software floating "
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"point features.">;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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// Floating Point, HW Division and Neon Support
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
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"Enable VFP3 instructions",
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[FeatureVFP2]>;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision "
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"floating point">;
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def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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"Enable VFP4 instructions",
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[FeatureVFP3, FeatureFP16]>;
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
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"true", "Enable ARMv8 FP",
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[FeatureVFP4]>;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Enable full half-precision "
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"floating point",
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[FeatureFPARMv8]>;
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def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
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"Floating point unit supports "
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"single precision only">;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict FP to 16 double registers">;
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def FeatureHWDivThumb : SubtargetFeature<"hwdiv",
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"HasHardwareDivideInThumb", "true",
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"Enable divide instructions in Thumb">;
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def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
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"HasHardwareDivideInARM", "true",
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"Enable divide instructions in ARM mode">;
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// Atomic Support
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb/dsb) instructions">;
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def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
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"Has v7 clrex instruction">;
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def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
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"HasAcquireRelease", "true",
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"Has v8 acquire/release (lda/ldaex "
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" etc) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable support for Performance "
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"Monitor extensions">;
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// TrustZone Security Extensions
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def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
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"Enable support for TrustZone "
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"security extensions">;
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def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
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"Enable support for ARMv8-M "
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"Security Extensions">;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable support for "
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"Cryptography extensions",
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[FeatureNEON]>;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable support for CRC instructions">;
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def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true",
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"Enable support for dot product instructions",
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[FeatureNEON]>;
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// Not to be confused with FeatureHasRetAddrStack (return address stack)
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable Reliability, Availability "
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"and Serviceability extensions">;
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// Fast computation of non-negative address offsets
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def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
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"Enable fast computation of "
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"positive address offsets">;
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// Fast execution of AES crypto operations
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def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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// The way of reading thread pointer
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def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
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"Reading thread pointer from register">;
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// Cyclone can zero VFP registers in 0 cycles.
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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// Whether it is profitable to unpredicate certain instructions during if-conversion
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def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
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"IsProfitableToUnpredicate", "true",
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"Is profitable to unpredicate">;
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// Some targets (e.g. Swift) have microcoded VGETLNi32.
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def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
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"HasSlowVGETLNi32", "true",
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"Has slow VGETLNi32 - prefer VMOV">;
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// Some targets (e.g. Swift) have microcoded VDUP32.
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def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
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"true",
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"Has slow VDUP32 - prefer VMOV">;
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// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
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// for scalar FP, as this allows more effective execution domain optimization.
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def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
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"true", "Prefer VMOVSR">;
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// Swift has ISHST barriers compatible with Atomic Release semantics but weaker
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// than ISH
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def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
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"true", "Prefer ISHST barriers">;
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// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
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def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits",
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"true",
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"Has muxed AGU and NEON/FPU">;
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// Whether VLDM/VSTM starting with odd register number need more microops
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// than single VLDRS
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def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
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"true", "VLDM/VSTM starting "
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"with an odd register is slow">;
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// Some targets have a renaming dependency when loading into D subregisters.
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def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
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"SlowLoadDSubregister", "true",
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"Loading into D subregs is slow">;
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// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
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def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
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"DontWidenVMOVS", "true",
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"Don't widen VMOVS to VMOVD">;
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// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
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def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx",
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"ExpandMLx", "true",
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"Expand VFP/NEON MLA/MLS instructions">;
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// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
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def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
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"true", "Has VMLx hazards">;
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// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
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// VFP to NEON, as an execution domain optimization.
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def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs",
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"UseNEONForFPMovs", "true",
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"Convert VMOVSR, VMOVRS, "
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"VMOVS to NEON">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations. This affects instruction selection and should
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// only be enabled if the handling of denormals is not important.
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def FeatureNEONForFP : SubtargetFeature<"neonfp",
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"UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// On some processors, VLDn instructions that access unaligned data take one
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// extra cycle. Take that into account when computing operand latencies.
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def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
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"true",
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"Check for VLDn unaligned access">;
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// Some processors have a nonpipelined VFP coprocessor.
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def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
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"NonpipelinedVFP", "true",
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"VFP instructions are not pipelined">;
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// Some processors have FP multiply-accumulate instructions that don't
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// play nicely with other VFP / NEON instructions, and it's generally better
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// to just not use them.
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def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
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"Disable VFP / NEON MAC instructions">;
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// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
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def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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/// Some instructions update CPSR partially, which can add false dependency for
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/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
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/// mapped to a separate physical register. Avoid partial CPSR update for these
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/// processors.
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def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
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"AvoidCPSRPartialUpdate", "true",
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"Avoid CPSR partial update for OOO execution">;
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/// Disable +1 predication cost for instructions updating CPSR.
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/// Enabled for Cortex-A57.
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def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
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"CheapPredicableCPSRDef",
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"true",
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"Disable +1 predication cost for instructions updating CPSR">;
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def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
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"AvoidMOVsShifterOperand", "true",
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"Avoid movs instructions with "
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"shifter operand">;
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// Some processors perform return stack prediction. CodeGen should avoid issue
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// "normal" call instructions to callees which do not return.
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def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
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"HasRetAddrStack", "true",
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"Has return address stack">;
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// Some processors have no branch predictor, which changes the expected cost of
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// taking a branch which affects the choice of whether to use predicated
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// instructions.
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def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
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"HasBranchPredictor", "false",
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"Has no branch predictor">;
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/// DSP extension.
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
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"Supports DSP instructions in "
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"ARM and/or Thumb2">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
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def FeatureVirtualization : SubtargetFeature<"virtualization",
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"HasVirtualization", "true",
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"Supports Virtualization extension",
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[FeatureHWDivThumb, FeatureHWDivARM]>;
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// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
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// See ARMInstrInfo.td for details.
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def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
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"NaCl trap">;
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
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"Generate calls via indirect call "
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"instructions">;
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def FeatureExecuteOnly : SubtargetFeature<"execute-only",
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"GenExecuteOnly", "true",
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"Enable the generation of "
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"execute only code.">;
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def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
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"Reserve R9, making it unavailable"
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" as GPR">;
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def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
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"Don't use movt/movw pairs for "
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"32-bit imms">;
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def FeatureNoNegativeImmediates
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: SubtargetFeature<"no-neg-immediates",
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"NegativeImmediates", "false",
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"Convert immediates and instructions "
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"to their negated or complemented "
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"equivalent when the immediate does "
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"not fit in the encoding.">;
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// Use the MachineScheduler for instruction scheduling for the subtarget.
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def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
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"Use the MachineScheduler">;
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//===----------------------------------------------------------------------===//
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// ARM architecture class
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//
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// A-series ISA
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def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
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"Is application profile ('A' series)">;
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// R-series ISA
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def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
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"Is realtime profile ('R' series)">;
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// M-series ISA
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def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
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"Is microcontroller profile ('M' series)">;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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"Does not support ARM mode execution">;
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//===----------------------------------------------------------------------===//
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// ARM ISAa.
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//
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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"Support ARM v4T instructions">;
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def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
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"Support ARM v5T instructions",
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[HasV4TOps]>;
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def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
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"Support ARM v5TE, v5TEj, and "
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"v5TExp instructions",
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[HasV5TOps]>;
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def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
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"Support ARM v6 instructions",
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[HasV5TEOps]>;
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def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
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"Support ARM v6M instructions",
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[HasV6Ops]>;
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def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
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"Support ARM v8M Baseline instructions",
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[HasV6MOps]>;
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def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
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"Support ARM v6k instructions",
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[HasV6Ops]>;
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def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
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"Support ARM v6t2 instructions",
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[HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
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def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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"Support ARM v7 instructions",
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[HasV6T2Ops, FeaturePerfMon,
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FeatureV7Clrex]>;
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def HasV8MMainlineOps :
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SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
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"Support ARM v8M Mainline instructions",
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[HasV7Ops]>;
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def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
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"Support ARM v8 instructions",
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[HasV7Ops, FeatureAcquireRelease]>;
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions",
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[HasV8Ops]>;
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def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
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"Support ARM v8.2a instructions",
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[HasV8_1aOps]>;
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def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
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"Support ARM v8.3a instructions",
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[HasV8_2aOps]>;
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//===----------------------------------------------------------------------===//
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// ARM Processor subtarget features.
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//
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def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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"Cortex-A5 ARM processors", []>;
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def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
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"Cortex-A7 ARM processors", []>;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors", []>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors", []>;
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def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
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"Cortex-A12 ARM processors", []>;
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def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
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"Cortex-A15 ARM processors", []>;
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def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
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"Cortex-A17 ARM processors", []>;
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def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
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"Cortex-A32 ARM processors", []>;
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def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
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"Cortex-A35 ARM processors", []>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors", []>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors", []>;
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def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
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"Cortex-A72 ARM processors", []>;
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def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
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"Cortex-A73 ARM processors", []>;
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def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
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"Qualcomm Krait processors", []>;
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def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
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"Qualcomm Kryo processors", []>;
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def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
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"Swift ARM processors", []>;
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def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
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"Samsung Exynos-Mx processors", []>;
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def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
|
|
"Cortex-R4 ARM processors", []>;
|
|
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
|
|
"Cortex-R5 ARM processors", []>;
|
|
def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
|
|
"Cortex-R7 ARM processors", []>;
|
|
def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
|
|
"Cortex-R52 ARM processors", []>;
|
|
|
|
def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
|
|
"Cortex-M3 ARM processors", []>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM Helper classes.
|
|
//
|
|
|
|
class Architecture<string fname, string aname, list<SubtargetFeature> features>
|
|
: SubtargetFeature<fname, "ARMArch", aname,
|
|
!strconcat(aname, " architecture"), features>;
|
|
|
|
class ProcNoItin<string Name, list<SubtargetFeature> Features>
|
|
: Processor<Name, NoItineraries, Features>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM architectures
|
|
//
|
|
|
|
def ARMv2 : Architecture<"armv2", "ARMv2", []>;
|
|
|
|
def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
|
|
|
|
def ARMv3 : Architecture<"armv3", "ARMv3", []>;
|
|
|
|
def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
|
|
|
|
def ARMv4 : Architecture<"armv4", "ARMv4", []>;
|
|
|
|
def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
|
|
|
|
def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
|
|
|
|
def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
|
|
|
|
def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
|
|
|
|
def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
|
|
|
|
def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
|
|
FeatureDSP]>;
|
|
|
|
def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
|
|
|
|
def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
|
|
FeatureTrustZone]>;
|
|
|
|
def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
|
|
FeatureNoARM,
|
|
ModeThumb,
|
|
FeatureDB,
|
|
FeatureMClass]>;
|
|
|
|
def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
|
|
FeatureNoARM,
|
|
ModeThumb,
|
|
FeatureDB,
|
|
FeatureMClass]>;
|
|
|
|
def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
|
|
FeatureNEON,
|
|
FeatureDB,
|
|
FeatureDSP,
|
|
FeatureAClass]>;
|
|
|
|
def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops,
|
|
FeatureNEON,
|
|
FeatureDB,
|
|
FeatureDSP,
|
|
FeatureTrustZone,
|
|
FeatureMP,
|
|
FeatureVirtualization,
|
|
FeatureAClass]>;
|
|
|
|
def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
|
|
FeatureDB,
|
|
FeatureDSP,
|
|
FeatureHWDivThumb,
|
|
FeatureRClass]>;
|
|
|
|
def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
|
|
FeatureThumb2,
|
|
FeatureNoARM,
|
|
ModeThumb,
|
|
FeatureDB,
|
|
FeatureHWDivThumb,
|
|
FeatureMClass]>;
|
|
|
|
def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
|
|
FeatureThumb2,
|
|
FeatureNoARM,
|
|
ModeThumb,
|
|
FeatureDB,
|
|
FeatureHWDivThumb,
|
|
FeatureMClass,
|
|
FeatureDSP]>;
|
|
|
|
def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
|
|
FeatureAClass,
|
|
FeatureDB,
|
|
FeatureFPARMv8,
|
|
FeatureNEON,
|
|
FeatureDSP,
|
|
FeatureTrustZone,
|
|
FeatureMP,
|
|
FeatureVirtualization,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
|
|
FeatureAClass,
|
|
FeatureDB,
|
|
FeatureFPARMv8,
|
|
FeatureNEON,
|
|
FeatureDSP,
|
|
FeatureTrustZone,
|
|
FeatureMP,
|
|
FeatureVirtualization,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
|
|
FeatureAClass,
|
|
FeatureDB,
|
|
FeatureFPARMv8,
|
|
FeatureNEON,
|
|
FeatureDSP,
|
|
FeatureTrustZone,
|
|
FeatureMP,
|
|
FeatureVirtualization,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureRAS]>;
|
|
|
|
def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps,
|
|
FeatureAClass,
|
|
FeatureDB,
|
|
FeatureFPARMv8,
|
|
FeatureNEON,
|
|
FeatureDSP,
|
|
FeatureTrustZone,
|
|
FeatureMP,
|
|
FeatureVirtualization,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureRAS]>;
|
|
|
|
def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
|
|
FeatureRClass,
|
|
FeatureDB,
|
|
FeatureDSP,
|
|
FeatureCRC,
|
|
FeatureMP,
|
|
FeatureVirtualization,
|
|
FeatureFPARMv8,
|
|
FeatureNEON]>;
|
|
|
|
def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
|
|
[HasV8MBaselineOps,
|
|
FeatureNoARM,
|
|
ModeThumb,
|
|
FeatureDB,
|
|
FeatureHWDivThumb,
|
|
FeatureV7Clrex,
|
|
Feature8MSecExt,
|
|
FeatureAcquireRelease,
|
|
FeatureMClass]>;
|
|
|
|
def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
|
|
[HasV8MMainlineOps,
|
|
FeatureNoARM,
|
|
ModeThumb,
|
|
FeatureDB,
|
|
FeatureHWDivThumb,
|
|
Feature8MSecExt,
|
|
FeatureAcquireRelease,
|
|
FeatureMClass]>;
|
|
|
|
// Aliases
|
|
def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
|
|
def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
|
|
def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
|
|
def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
|
|
def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
|
|
def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM schedules.
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
include "ARMSchedule.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM processors
|
|
//
|
|
|
|
// Dummy CPU, used to target architectures
|
|
def : ProcessorModel<"generic", CortexA8Model, []>;
|
|
|
|
// FIXME: Several processors below are not using their own scheduler
|
|
// model, but one of similar/previous processor. These should be fixed.
|
|
|
|
def : ProcNoItin<"arm8", [ARMv4]>;
|
|
def : ProcNoItin<"arm810", [ARMv4]>;
|
|
def : ProcNoItin<"strongarm", [ARMv4]>;
|
|
def : ProcNoItin<"strongarm110", [ARMv4]>;
|
|
def : ProcNoItin<"strongarm1100", [ARMv4]>;
|
|
def : ProcNoItin<"strongarm1110", [ARMv4]>;
|
|
|
|
def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
|
|
def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
|
|
def : ProcNoItin<"arm710t", [ARMv4t]>;
|
|
def : ProcNoItin<"arm720t", [ARMv4t]>;
|
|
def : ProcNoItin<"arm9", [ARMv4t]>;
|
|
def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
|
|
def : ProcNoItin<"arm920", [ARMv4t]>;
|
|
def : ProcNoItin<"arm920t", [ARMv4t]>;
|
|
def : ProcNoItin<"arm922t", [ARMv4t]>;
|
|
def : ProcNoItin<"arm940t", [ARMv4t]>;
|
|
def : ProcNoItin<"ep9312", [ARMv4t]>;
|
|
|
|
def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
|
|
def : ProcNoItin<"arm1020t", [ARMv5t]>;
|
|
|
|
def : ProcNoItin<"arm9e", [ARMv5te]>;
|
|
def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
|
|
def : ProcNoItin<"arm946e-s", [ARMv5te]>;
|
|
def : ProcNoItin<"arm966e-s", [ARMv5te]>;
|
|
def : ProcNoItin<"arm968e-s", [ARMv5te]>;
|
|
def : ProcNoItin<"arm10e", [ARMv5te]>;
|
|
def : ProcNoItin<"arm1020e", [ARMv5te]>;
|
|
def : ProcNoItin<"arm1022e", [ARMv5te]>;
|
|
def : ProcNoItin<"xscale", [ARMv5te]>;
|
|
def : ProcNoItin<"iwmmxt", [ARMv5te]>;
|
|
|
|
def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
|
|
def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
|
|
FeatureVFP2,
|
|
FeatureHasSlowFPVMLx]>;
|
|
|
|
def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
|
|
def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
|
|
def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
|
|
def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
|
|
|
|
def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>;
|
|
def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
|
|
def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
|
|
FeatureVFP2,
|
|
FeatureHasSlowFPVMLx]>;
|
|
|
|
def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
|
|
def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
|
|
FeatureVFP2,
|
|
FeatureHasSlowFPVMLx]>;
|
|
|
|
def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
|
|
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
|
|
FeatureVFP2,
|
|
FeatureHasSlowFPVMLx]>;
|
|
|
|
def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
|
|
FeatureHasRetAddrStack,
|
|
FeatureTrustZone,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureVMLxForwarding,
|
|
FeatureMP,
|
|
FeatureVFP4]>;
|
|
|
|
def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
|
|
FeatureHasRetAddrStack,
|
|
FeatureTrustZone,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHasVMLxHazards,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureVMLxForwarding,
|
|
FeatureMP,
|
|
FeatureVFP4,
|
|
FeatureVirtualization]>;
|
|
|
|
def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
|
|
FeatureHasRetAddrStack,
|
|
FeatureNonpipelinedVFP,
|
|
FeatureTrustZone,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHasVMLxHazards,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureVMLxForwarding]>;
|
|
|
|
def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
|
|
FeatureHasRetAddrStack,
|
|
FeatureTrustZone,
|
|
FeatureHasVMLxHazards,
|
|
FeatureVMLxForwarding,
|
|
FeatureFP16,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureExpandMLx,
|
|
FeaturePreferVMOVSR,
|
|
FeatureMuxedUnits,
|
|
FeatureNEONForFPMovs,
|
|
FeatureCheckVLDnAlign,
|
|
FeatureMP]>;
|
|
|
|
def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
|
|
FeatureHasRetAddrStack,
|
|
FeatureTrustZone,
|
|
FeatureVMLxForwarding,
|
|
FeatureVFP4,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureVirtualization,
|
|
FeatureMP]>;
|
|
|
|
def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
|
|
FeatureDontWidenVMOVS,
|
|
FeatureHasRetAddrStack,
|
|
FeatureMuxedUnits,
|
|
FeatureTrustZone,
|
|
FeatureVFP4,
|
|
FeatureMP,
|
|
FeatureCheckVLDnAlign,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureVirtualization]>;
|
|
|
|
def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
|
|
FeatureHasRetAddrStack,
|
|
FeatureTrustZone,
|
|
FeatureMP,
|
|
FeatureVMLxForwarding,
|
|
FeatureVFP4,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureVirtualization]>;
|
|
|
|
// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv
|
|
def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
|
|
FeatureHasRetAddrStack,
|
|
FeatureMuxedUnits,
|
|
FeatureCheckVLDnAlign,
|
|
FeatureVMLxForwarding,
|
|
FeatureFP16,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureVFP4,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM]>;
|
|
|
|
def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
|
|
FeatureHasRetAddrStack,
|
|
FeatureNEONForFP,
|
|
FeatureVFP4,
|
|
FeatureMP,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureAvoidMOVsShOp,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureHasVMLxHazards,
|
|
FeatureProfUnpredicate,
|
|
FeaturePrefISHSTBarrier,
|
|
FeatureSlowOddRegister,
|
|
FeatureSlowLoadDSubreg,
|
|
FeatureSlowVGETLNi32,
|
|
FeatureSlowVDUP32,
|
|
FeatureUseMISched]>;
|
|
|
|
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
|
|
FeatureHasRetAddrStack,
|
|
FeatureAvoidPartialCPSR]>;
|
|
|
|
def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
|
|
FeatureHasRetAddrStack,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureVFP3,
|
|
FeatureD16,
|
|
FeatureAvoidPartialCPSR]>;
|
|
|
|
def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
|
|
FeatureHasRetAddrStack,
|
|
FeatureVFP3,
|
|
FeatureD16,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHWDivARM,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureAvoidPartialCPSR]>;
|
|
|
|
def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
|
|
FeatureHasRetAddrStack,
|
|
FeatureVFP3,
|
|
FeatureD16,
|
|
FeatureFP16,
|
|
FeatureMP,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHWDivARM,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureAvoidPartialCPSR]>;
|
|
|
|
def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
|
|
FeatureHasRetAddrStack,
|
|
FeatureVFP3,
|
|
FeatureD16,
|
|
FeatureFP16,
|
|
FeatureMP,
|
|
FeatureSlowFPBrcc,
|
|
FeatureHWDivARM,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureAvoidPartialCPSR]>;
|
|
|
|
def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m,
|
|
ProcM3,
|
|
FeatureHasNoBranchPredictor]>;
|
|
|
|
def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m,
|
|
ProcM3,
|
|
FeatureHasNoBranchPredictor]>;
|
|
|
|
def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em,
|
|
FeatureVFP4,
|
|
FeatureVFPOnlySP,
|
|
FeatureD16,
|
|
FeatureHasNoBranchPredictor]>;
|
|
|
|
def : ProcNoItin<"cortex-m7", [ARMv7em,
|
|
FeatureFPARMv8,
|
|
FeatureD16]>;
|
|
|
|
def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
|
|
FeatureNoMovt]>;
|
|
|
|
def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline,
|
|
FeatureDSP,
|
|
FeatureFPARMv8,
|
|
FeatureD16,
|
|
FeatureVFPOnlySP,
|
|
FeatureHasNoBranchPredictor]>;
|
|
|
|
def : ProcNoItin<"cortex-a32", [ARMv8a,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFPAO]>;
|
|
|
|
def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFPAO,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureCheapPredicableCPSR]>;
|
|
|
|
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
|
|
FeatureHasRetAddrStack,
|
|
FeatureNEONForFP,
|
|
FeatureVFP4,
|
|
FeatureMP,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureAvoidMOVsShOp,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureCrypto,
|
|
FeatureUseMISched,
|
|
FeatureZCZeroing]>;
|
|
|
|
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
|
|
FeatureFPAO]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARMRegisterInfo.td"
|
|
include "ARMRegisterBanks.td"
|
|
include "ARMCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARMInstrInfo.td"
|
|
def ARMInstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declare the target which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ARMAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
int PassSubtarget = 1;
|
|
int Variant = 0;
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
def ARMAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
string Name = "ARM";
|
|
string BreakCharacters = ".";
|
|
}
|
|
|
|
def ARM : Target {
|
|
// Pull in Instruction Info.
|
|
let InstructionSet = ARMInstrInfo;
|
|
let AssemblyWriters = [ARMAsmWriter];
|
|
let AssemblyParserVariants = [ARMAsmParserVariant];
|
|
}
|