247 lines
6.6 KiB
LLVM
247 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (sub x, 0) -> x
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define <4 x i32> @combine_vec_sub_zero(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_zero:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_zero:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %a, zeroinitializer
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ret <4 x i32> %1
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}
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; fold (sub x, x) -> 0
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define <4 x i32> @combine_vec_sub_self(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_self:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_self:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %a, %a
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ret <4 x i32> %1
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}
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; fold (sub x, c) -> (add x, -c)
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define <4 x i32> @combine_vec_sub_constant(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sub_constant:
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; SSE: # BB#0:
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; SSE-NEXT: psubd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_constant:
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; AVX: # BB#0:
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; AVX-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %1
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}
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; Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
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define <4 x i32> @combine_vec_sub_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sub_negone:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_negone:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
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ret <4 x i32> %1
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}
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; fold A-(A-B) -> B
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define <4 x i32> @combine_vec_sub_sub(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: combine_vec_sub_sub:
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; SSE: # BB#0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_sub:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %a, %b
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%2 = sub <4 x i32> %a, %1
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ret <4 x i32> %2
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}
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; fold (A+B)-A -> B
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define <4 x i32> @combine_vec_sub_add0(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: combine_vec_sub_add0:
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; SSE: # BB#0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add0:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %a, %b
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%2 = sub <4 x i32> %1, %a
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ret <4 x i32> %2
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}
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; fold (A+B)-B -> A
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define <4 x i32> @combine_vec_sub_add1(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: combine_vec_sub_add1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = add <4 x i32> %a, %b
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%2 = sub <4 x i32> %1, %b
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ret <4 x i32> %2
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}
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; fold C2-(A+C1) -> (C2-C1)-A
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define <4 x i32> @combine_vec_sub_constant_add(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_constant_add:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa {{.*#+}} xmm1 = [3,1,4294967295,4294967293]
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_constant_add:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [3,1,4294967295,4294967293]
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %a, <i32 0, i32 1, i32 2, i32 3>
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%2 = sub <4 x i32> <i32 3, i32 2, i32 1, i32 0>, %1
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ret <4 x i32> %2
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}
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; fold ((A+(B+C))-B) -> A+C
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define <4 x i32> @combine_vec_sub_add_add(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_vec_sub_add_add:
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; SSE: # BB#0:
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; SSE-NEXT: paddd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add_add:
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; AVX: # BB#0:
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; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %b, %c
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%2 = add <4 x i32> %a, %1
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%3 = sub <4 x i32> %2, %b
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ret <4 x i32> %3
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}
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; fold ((A+(B-C))-B) -> A-C
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define <4 x i32> @combine_vec_sub_add_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_vec_sub_add_sub:
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; SSE: # BB#0:
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; SSE-NEXT: psubd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add_sub:
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; AVX: # BB#0:
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; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %b, %c
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%2 = add <4 x i32> %a, %1
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%3 = sub <4 x i32> %2, %b
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ret <4 x i32> %3
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}
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; fold ((A-(B-C))-C) -> A-B
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define <4 x i32> @combine_vec_sub_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_vec_sub_sub_sub:
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; SSE: # BB#0:
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_sub_sub:
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; AVX: # BB#0:
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %b, %c
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%2 = sub <4 x i32> %a, %1
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%3 = sub <4 x i32> %2, %c
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ret <4 x i32> %3
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}
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; fold undef-A -> undef
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define <4 x i32> @combine_vec_sub_undef0(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_undef0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_undef0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = sub <4 x i32> undef, %a
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ret <4 x i32> %1
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}
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; fold A-undef -> undef
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define <4 x i32> @combine_vec_sub_undef1(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_undef1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_undef1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %a, undef
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ret <4 x i32> %1
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}
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; sub X, (sext Y i1) -> add X, (and Y 1)
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define <4 x i32> @combine_vec_add_sext(<4 x i32> %x, <4 x i1> %y) {
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; SSE-LABEL: combine_vec_add_sext:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $31, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_add_sext:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $31, %xmm1, %xmm1
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; AVX-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sext <4 x i1> %y to <4 x i32>
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%2 = sub <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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; sub X, (sextinreg Y i1) -> add X, (and Y 1)
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define <4 x i32> @combine_vec_sub_sextinreg(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_sub_sextinreg:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $31, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_sextinreg:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $31, %xmm1, %xmm1
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; AVX-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %y, <i32 31, i32 31, i32 31, i32 31>
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%2 = ashr <4 x i32> %1, <i32 31, i32 31, i32 31, i32 31>
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%3 = sub <4 x i32> %x, %2
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ret <4 x i32> %3
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}
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