227 lines
9.0 KiB
LLVM
227 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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; fold (udiv undef, x) -> 0
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define <4 x i32> @combine_vec_udiv_undef0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_undef0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_undef0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> undef, %x
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ret <4 x i32> %1
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}
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; fold (udiv x, undef) -> undef
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define <4 x i32> @combine_vec_udiv_undef1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_undef1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_undef1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> %x, undef
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ret <4 x i32> %1
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}
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; fold (udiv x, (1 << c)) -> x >>u c
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define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_by_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_by_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_udiv_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_by_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrld $3, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; SSE-NEXT: psrld $4, %xmm0
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; SSE-NEXT: psrld $2, %xmm2
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; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_udiv_by_pow2b:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpsrld $4, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $2, %xmm0, %xmm2
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: vpsrld $3, %xmm0, %xmm2
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_udiv_by_pow2b:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = udiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_udiv_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_udiv_by_pow2c:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: movdqa %xmm0, %xmm3
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; SSE-NEXT: psrld %xmm2, %xmm3
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrlq $32, %xmm2
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; SSE-NEXT: movdqa %xmm0, %xmm4
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; SSE-NEXT: psrld %xmm2, %xmm4
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; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
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; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrld %xmm1, %xmm2
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; SSE-NEXT: psrld %xmm3, %xmm0
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_udiv_by_pow2c:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
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; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
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; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
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; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_udiv_by_pow2c:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
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%2 = udiv <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
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define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_udiv_by_shl_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: movdqa %xmm0, %xmm3
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; SSE-NEXT: psrld %xmm2, %xmm3
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrlq $32, %xmm2
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; SSE-NEXT: movdqa %xmm0, %xmm4
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; SSE-NEXT: psrld %xmm2, %xmm4
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; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
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; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrld %xmm1, %xmm2
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; SSE-NEXT: psrld %xmm3, %xmm0
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_udiv_by_shl_pow2a:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
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; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
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; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
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; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_udiv_by_shl_pow2a:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2,2,2,2]
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; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
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%2 = udiv <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_udiv_by_shl_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: movdqa %xmm0, %xmm3
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; SSE-NEXT: psrld %xmm2, %xmm3
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrlq $32, %xmm2
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; SSE-NEXT: movdqa %xmm0, %xmm4
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; SSE-NEXT: psrld %xmm2, %xmm4
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; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
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; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrld %xmm1, %xmm2
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; SSE-NEXT: psrld %xmm3, %xmm0
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_udiv_by_shl_pow2b:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
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; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
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; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
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; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_udiv_by_shl_pow2b:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
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%2 = udiv <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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