a7cb31123c
Summary: Starting from GCN 2nd generation, ISA supports ds_read_b128 on top of ds_read_b64.
This patch supports ds_read_b128 instruction pattern and generation of this instruction.
In the vectorizer, this patch also widen the vector length so that vectorizer generates
128 bit loads for local address-space which gets translated to ds_read_b128.
Since the performance benefit is not clear; compiler generates ds_read_b128 under -amdgpu-ds128.
Author: FarhanaAleen
Reviewed By: rampitec, arsenm
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44210
llvm-svn: 327153
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| .. | ||
| aa-metadata.ll | ||
| adjust-alloca-alignment.ll | ||
| extended-index.ll | ||
| gep-bitcast.ll | ||
| insertion-point.ll | ||
| interleaved-mayalias-store.ll | ||
| lit.local.cfg | ||
| merge-stores-private.ll | ||
| merge-stores.ll | ||
| merge-vectors.ll | ||
| missing-alignment.ll | ||
| multiple_tails.ll | ||
| no-implicit-float.ll | ||
| optnone.ll | ||
| pointer-elements.ll | ||
| store_with_aliasing_load.ll | ||
| weird-type-accesses.ll | ||