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AsmParser
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[RISCV] AsmParser support for the li pseudo instruction
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2018-06-07 15:35:47 +00:00 |
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Disassembler
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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InstPrinter
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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MCTargetDesc
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[RISCV] Tail calls don't need to save return address
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2018-06-21 14:37:09 +00:00 |
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TargetInfo
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Fix RISCV build after r318352
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2017-11-16 18:39:31 +00:00 |
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CMakeLists.txt
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[RISCV] Add machine function pass to merge base + offset
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2018-06-27 20:51:42 +00:00 |
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LLVMBuild.txt
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCV.h
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[RISCV] Add machine function pass to merge base + offset
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2018-06-27 20:51:42 +00:00 |
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RISCV.td
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[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation
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2018-05-15 01:28:50 +00:00 |
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RISCVAsmPrinter.cpp
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Revert "[RISCV] implement li pseudo instruction"
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2018-04-18 19:02:31 +00:00 |
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RISCVCallingConv.td
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVFrameLowering.cpp
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVFrameLowering.h
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[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
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2018-03-20 01:39:17 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Add machine function pass to merge base + offset
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2018-06-27 20:51:42 +00:00 |
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RISCVISelLowering.cpp
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVISelLowering.h
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVInstrFormats.td
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[RISCV] AsmParser support for the li pseudo instruction
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2018-06-07 15:35:47 +00:00 |
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RISCVInstrFormatsC.td
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[RISCV] MC layer support for the remaining RVC instructions
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2017-12-13 09:32:55 +00:00 |
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RISCVInstrInfo.cpp
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVInstrInfo.h
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[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
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2018-04-26 15:34:27 +00:00 |
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RISCVInstrInfo.td
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVInstrInfoA.td
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[RISCV] Add codegen support for atomic load/stores with RV32A
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2018-06-13 12:04:51 +00:00 |
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RISCVInstrInfoC.td
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[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
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2018-04-12 19:22:40 +00:00 |
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RISCVInstrInfoD.td
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[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}
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2018-06-20 14:03:02 +00:00 |
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RISCVInstrInfoF.td
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[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w
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2018-06-20 18:42:25 +00:00 |
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RISCVInstrInfoM.td
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[RISCV] Codegen support for the standard RV32M instruction set extension
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2018-01-18 12:36:38 +00:00 |
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RISCVMCInstLower.cpp
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[RISCV] Add codegen for RV32F floating point load/store
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2018-03-20 13:26:12 +00:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
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2018-04-12 05:34:25 +00:00 |
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RISCVMergeBaseOffset.cpp
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Test commit.
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2018-08-02 05:38:18 +00:00 |
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RISCVRegisterInfo.cpp
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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RISCVRegisterInfo.h
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[RISCV] Set isReMaterializable on ADDI and LUI instructions
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2018-05-17 15:51:37 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Lower the tail pseudoinstruction
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2018-05-23 22:44:08 +00:00 |
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RISCVSubtarget.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVSubtarget.h
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[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation
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2018-05-15 01:28:50 +00:00 |
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RISCVTargetMachine.cpp
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[RISCV] Add machine function pass to merge base + offset
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2018-06-27 20:51:42 +00:00 |
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RISCVTargetMachine.h
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVTargetObjectFile.cpp
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
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RISCVTargetObjectFile.h
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
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